AD4884BBCZ datasheet(29/116 Pages) AD

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Data Sheet

AD4884

THEORY OF OPERATION

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Rev. 0 | 29 of 116

Figure 51. Typical Regulator Start-Up Transient, Converter Idle

The required connectivity when using the internal regulators is

shown in Figure 52. As shown in Figure 52, the three VDD11ChA

pins (G7, H7, and J7) must be shorted. It is recommended that

a thick trace or polygon on the device side of the PCB be used

to implement this connection in the physical design to minimize

routing impedance. The same shorting indications apply to the

VDD11ChB pins (G14, H14, and J14). The VDD33 rail must be

powered with an external 3.3V supply. To further minimize power

consumption, this supply can be removed when both channels have

been put in one of the power saving modes. When this supply is

removed, only analog circuity is held in reset, and the configuration

age tolerance for each supply rail, see the Specifications section.

Figure 52. Internally Regulated (1.1V) Supply Configuration

The internally regulated configuration is ideal for use in area

constrained applications where the ability to eliminate external

regulators is advantageous. However, note that in this configuration

the internal regulators introduce additional power dissipation inside

AD4884.

EXTERNALLY GENERATED SUPPLY

CONFIGURATION

In systems using externally generated supplies, VDDLDO pins must

be left unconnected. With VDDLDO unconnected, all four internal

LDO regulators powering VDD11ChA, VDD11ChB, IOVDDDChA, and

IOVDDDChB are automatically disabled. VDD11ChA and VDD11ChB

must be externally supplied with 1.1 V, it is recommended to supply

both rails with the same source. IOVDDChA and IOVDDChA must

be externally supplied with 1.1V to 1.2V, it is recommended to

supply both rails with the same source. Note that if VDD11ChX is

not present, the corresponding ADC channel is held in a POR

state and all its registers reset to their default state after the

supply reestablishes. For more details on the POR circuitry, see the

Power-On Reset (POR) Monitor section. The VDD33 rail must be

powered with an external 3.3V supply. The VDD33 supply can be

removed to further reduce power when both channels are in one of

the two Power Saving Operating Modes, only analog circuity is held

in reset, and register contents remain unaffected. For the applicable

input voltage tolerance for each supply rail, see the Specifications

section.

As shown in the example of Figure 53, external voltage sources

are applied to VDD11ChA, VDD11ChB, IOVDDDChA, and IOVDDDChB

pins.

Figure 53. Externally Sourced Supply Configuration

POWER-ON RESET (POR) MONITOR

Each AD4884 channel has an independent power supply monitor-

ing circuit that inhibits the converter functions and resets the config-

uration memory when supply conditions are outside the specified

operating limits. This function ensures that the channel is in a deter-

ministic state after power-up. The power-on function is constructed

from two independent voltage monitors, the first measuring the core

1.1V supply (VDD11ChX) and a second measuring the voltage at

the reference input (REFIN). Each monitor has its own comparator

output that is used to decouple the analog and digital block resets,

as shown in Figure 54.

Figure 54. Simplified Diagram of POR Circuit (Shown for Channel A)

The core VDD (1.1V) supply monitor compares the VDD11ChX sup-

ply voltage against a preset threshold of 0.93V. If the supply voltage

falls to less than this threshold, a reset signal, POR_D, asserts.

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