AD4884BBCZ datasheet(52/116 Pages) AD

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Data Sheet

AD4884

DIGITAL INTERFACE

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Rev. 0 | 52 of 116

(ADDRESS) and the most significant byte of the multibyte register

resides in the least significant address of the register segment. By

default, the ADDR_ASCENSION property is set to descending, indi-

cating that the address for the most significant register is passed

to the host controller during the instruction phase. Depending on

the selected operation, the instruction word is followed by either a

payload consisting of data for the byte-wide register (DATA), least

significant bytes (LSBYTE), and most significant bytes (MSBYTE)

of the multibyte register, or, in the case of a read access, padding

bits. As a convention, it is recommended to pass Logic 1 to SDI

during a read access to avoid accidentally addressing address zero

for write access.

In single instruction mode (SINGLE_INST = 1), the memory access

controller requires an instruction phase to transmit for each register

accessed in a given SPI frame, as shown in Figure 92. This mode

is useful when access to nonadjacent sections of the register space

is required in a given SPI frame. Note that, the same access

flexibility can be achieved in stream mode by initiating a new SPI

frame for each unique register access.

The single instruction mode is selected by setting SINGLE_INST

= 1 in the Interface Configuration B register (see the Interface

Configuration B Register section, Address 0x01).

Figure 91. Interface Access Example, Default Interface Configuration, Streaming Mode (ADDR_ASCENSION = 0)

Figure 92. Interface Access Example, Single Instruction Mode (SINGLE_INST = 1), All Other Interface Options Default

Address Ascension Selection

The address ascension selection (ADDR_ASCENSION) bit, as de-

scribed in previous sections, determines how the internal interface

address pointer is updated for each byte of data transmitted to the

AD4884 channel in streaming mode (SINGLE_INST = 0). If using

single instruction mode (SINGLE_INST = 1), each register is direct-

ly addressed through its own instruction phase, as shown in Figure

92, and thus, the address pointer is not updated. Regardless of

the setting for SINGLE_INST, the ADDR_ASCENSION bit directly

impacts the formatting of the SPI frame in terms of selection of

the instruction phase starting address and byte order of the data

phase payload. This impact is described in greater detail in the

Strict Access Selection and Multibyte Registers section as much

of the data formatting is dependent on this interface configuration

selection. The ADDR_ASCENSION selection bit is located in the

Interface Configuration A register (see the Interface Configuration A

As summarized in Table 15, the ADDR_ASCENSION bit is cleared

by default, resulting in the address pointer decrementing by one

for each data byte transmitted. In this decrement configuration

(ADDR_ASCENSION = 0), the address pointer decrements from

the starting address indicated in the instruction phase by one for

each data phase byte received until the counter reaches Address

0x0000. If additional bytes are received, the pointer automatically

rolls over to the maximum address value, 0x7FFF, the rollover

behavior is fixed, and therefore, independent of the SHORT_IN-

STRUCTION value or the physical address space occupied by the

user configurable registers. It is important to understand this behav-

ior to avoid generating interface errors associated with attempting

to access one or more invalid register addresses. Limit register

access to the register address space associated with the device

configuration as described in the Configuration Registers section.

Alternatively, the ADDR_ASCENSION bit can be set (ADDR_AS-

CENSION = 1), resulting in the address pointer incrementing by

one, starting at the address identified in the instruction word, for

each data phase byte received at the AD4884 in a given SPI

frame. In a manner similar to the descending case, the address

counter continues to increment for each data byte received until

the maximum address value, 0x7FFFF, is reached, after which the

pointer rolls over to 0x0000.

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