AD4884BBCZ datasheet(75/116 Pages) AD

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Data Sheet

AD4884

DIGITAL FEATURES

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Rev. 0 | 75 of 116

Threshold Detect Levels

The threshold detection of the AD4884 includes a hysteresis set-

ting. By configuring this setting, the user can ensure that unwanted

threshold triggering can be avoided. Figure 120 shows how this

can be achieved. A single hysteresis setting is configured, that is

then applied to both the HI_THRESHOLD and LO_THRESHOLD

bits. The high and low detection flags remain set until the hysteresis

thresholds are crossed.

Figure 120. Threshold Detect Levels

Enabling Event Detection

By default, after power on or reset, HI_ROUTE and LO_ROUTE

are set to Logic 0, masking the threshold level detection from

generating any event alert. When enabled, the gated versions of

these signals, HI_DTCT_GATED and LO_DTCT_GATED, are logic

NOR'd to generate the ALERT signal. If a user requires the use

of the HI_DTCT, LO_DTCT, or ALERT signals to flag an event

occurrence externally, back to a digital host, the GPIO_x_SEL

registers can be used to route any, or multiple, of these signals to

the GPIO pins.

Event Detection for FIFO

Event detection can also be used in a channel to arm its FIFO

memory. The event detection for the FIFO can be triggered using

either internal or external events as detailed in the Table 26 section.

To use the ALERT signal to trigger the FIFO, the HI_ROUTE

and/or the LO_ROUTE bits must be configured as required, and

the INT_EVENT_EN bit must be set to 1, to use a combined

ALERT output to trigger the FIFO. Alternately, when configured

with the INT_EVENT_EN bit set to 0, a GPIO EXT_EVENT input

must be configured, and this input triggers the FIFO when a Logic

1 is presented on the GPIO. Because this event was generated

externally, there is no ALERT signal generated.

The HI_THRESHOLD (Address 021 and Address 022) and

LO_THRESHOLD (Address 0x23 and Address 0x 24) bits can

be used to configure the ADC output code thresholds for the

internal event detection. These bits can each be masked using

the HI_ROUTE and LO_ROUTE bits in the general configuration

bits to be used for the ALERT flag (that can be monitored using

a preconfigured GPIO), it is also enabled as a FIFO event trigger

as well as making these available as HI_STATUS and LO_STATUS

flags in the device status register (Address 0x14).

Figure 121. FIFO Event Detection Logic

Event Detection ADC Data Result

The ADC data result, as shown in Figure 118, is dependent of the

selected data path. As is evident in Figure 132, where the digital

filter (see the Digital Filter section) is enabled, the output of the

selected filter refers to the ADC data result that is checked by the

threshold detection for event detection.

RESULT FIFO

Each AD4884 channel has an independent single port data FIFO

for applications where a reduced data interface transmission load

is required and where asynchronous data capture and access is

appropriate. This FIFO can serve to reduce the requirements for

the digital host controller and can, for example, enable the AD4884

to be deployed in systems using an MCU digital host. Each data

FIFO allows for a record of up to 16,384 data results to be captured

per acquisition burst without result loss due to data overflow. As

a single port memory, simultaneous data interface read and ADC

conversion result write operations are not permitted to the FIFO.

To allow synchronization of FIFO access between the host control-

ler and ADC, status flags are included to indicate if the memory

is full (FIFO_FULL) or if no new data available in the FIFO

(FIFO_READ_DONE), that is, there is no new data since the last

trigger is set, or the last FIFO data read back of a result record

has already been completed. When N = WATERMARK is reached,

that is, when the conversion result corresponding to the specified

count in the FIFO_WATERMARK register is loaded into the data

FIFO, memory is set as full, and the FIFO_FULL bit gets asserted

in device status register (see the Device Status Register section,

Address 0x4). The status bits can be accessed by reading directly

from the device status register (Address 0x14) via the configuration

SPI, appending the status to the data SPI frame, or by assigning

the required status flags to a GPIO pin by setting the required

GPIO_x_SEL bit. For more details on these GPIO, see the GPIO

Pins section. The user can also select between various modes of

initiating the burst acquisition, which is described further in the FIFO

Mode Selection and Configuration section.

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