AD4884BBCZ datasheet(104/116 Pages) AD

104 / 116 page

Data Sheet

AD4884

CONFIGURATION REGISTERS

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Rev. 0 | 104 of 116

ADC Data Interface Configuration A Register

Address: 0x15, Reset: 0x40, Name: ADC_DATA_INTF_CONFIG_A

Figure 162. ADC Data Interface Configuration A Register

Table 48. Bit Descriptions for ADC_DATA_INTF_CONFIG_A

Bits

Bit Name

Description

Reset

Access

RESERVED

Reserved. Write 0b0 to this bit.

0x0

RESERVED

Reserved. Always set this bit to 1.

0x1

R/W

RESERVED

Reserved. Write 0b0 to this bit.

0x0

INTF_CHK_EN

Output Fixed Test Pattern on the Data Interface of the channel (LVDS Only). ADC output is not available when

this mode is enabled. Fixed pattern = 16'b1010 1100 0101 1101 (0xAC5D).

0x0

R/W

0: Test Pattern Disabled.

1: Test Pattern Enabled.

RESERVED

Reserved. Write 0b0 to this bit.

0x0

SPI_LVDS_LANES

LVDS/SPI Lane Control. Determines the number of lanes that the conversion data of the channel is clocked out

on.

0x0

R/W

0: One Lane Active.

1: Multiple Lanes Active (Two for LVDS and Four for the SPI Data Interface).

RESERVED

Reserved. Write 0b0 to this bit.

0x0

DATA_INTF_MODE

Read Conversion Data Over SPI or LVDS. Acts as global LVDS enable, setting this bit to 1 powers down the

LVDS transmitters/receivers.

0x0

R/W

0: Data Read Back Over LVDS.

1: Data Read Back Over SPI Data Interface (DCSChX/DCLKChX). CLK+ChX is repurposed as the SPI data

interface clock (DCLKChX) for reading FIFO data, and CLK−ChX is repurposed as the SPI chip select (DCSChX)

for reading FIFO data.

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