HCS08 datasheet(204/290 Pages) MOTOROLA

204 / 290 page

Serial Peripheral Interface (SPI) Module

MC9S08GB/GT

204

MOTOROLA

SPR2:SPR1:SPR0 — SPI Baud Rate Divisor

This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in Table 12-3. The

input to this divider comes from the SPI baud rate prescaler (see Figure 12-4). The output of this

divider is the SPI bit rate clock for master mode.

12.4.4 SPI Status Register (SPIS)

This register has three read-only status bits. Bits 6, 3, 2, 1, and 0 are not implemented and always read 0s.

Writes have no meaning or effect.

Figure 12-10 SPI Status Register (SPIS)

SPRF — SPI Read Buffer Full Flag

SPRF is set at the completion of an SPI transfer to indicate that received data may be read from the SPI

data register (SPID). SPRF is cleared by reading SPRF while it is set, then reading the SPI data register.

1 = Data available in the receive data buffer.

0 = No data available in the receive data buffer.

Table 12-3 SPI Baud Rate Divisor

SPR2:SPR1:SPR0

Rate Divisor

0:0:0

0:0:1

0:1:0

0:1:1

1:0:0

1:0:1

1:1:0

128

1:1:1

256

Bit 7

654321

Bit 0

Read:

SPRF

SPTEF

MODF

0000

Write:

Reset:

00100000

= Unimplemented or Reserved

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