HCS08 datasheet(201/290 Pages) MOTOROLA

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Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

201

MC9S08GB/GT

SPTIE — SPI Transmit Interrupt Enable

This is the interrupt enable bit for SPI transmit buffer empty (SPTEF).

1 = When SPTEF is 1, hardware interrupt requested.

0 = Interrupts from SPTEF inhibited (use polling).

MSTR — Master/Slave Mode Select

1 = SPI module configured as a master SPI device.

0 = SPI module configured as a slave SPI device.

CPOL — Clock Polarity

This bit effectively places an inverter in series with the clock signal from a master SPI or to a slave SPI

device. Refer to 12.3.1 SPI Clock Formats for more details.

1 = Active-low SPI clock (idles high).

0 = Active-high SPI clock (idles low).

CPHA — Clock Phase

This bit selects one of two clock formats for different kinds of synchronous serial peripheral devices.

Refer to 12.3.1 SPI Clock Formats for more details.

1 = First edge on SPSCK occurs at the start of the first cycle of an 8-cycle data transfer.

0 = First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer.

SSOE — Slave Select Output Enable

This bit is used in combination with the mode fault enable (MODFEN) bit in SPCR2 and the

master/slave (MSTR) control bit to determine the function of the SS pin as shown in Table 12-1.

LSBFE — LSB First (Shifter Direction)

1 = SPI serial data transfers start with least significant bit.

0 = SPI serial data transfers start with most significant bit.

Table 12-1 SS Pin Function

MODFEN

SSOE

Master Mode

Slave Mode

General-purpose I/O (not SPI)

Slave select input

General-purpose I/O (not SPI)

Slave select input

SS input for mode fault

Slave select input

Automatic SS output

Slave select input

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