HCS08 datasheet(200/290 Pages) MOTOROLA

200 / 290 page

Serial Peripheral Interface (SPI) Module

MC9S08GB/GT

200

MOTOROLA

When a mode fault is detected, MODF is set and MSTR is cleared to change the SPI configuration back

to slave mode. The output drivers on the SPSCK, MOSI, and MISO (if not bidirectional mode) are

disabled.

MODF is cleared by reading it while it is set, then writing to the SPI control register 1 (SPIC1). User

software should verify the error condition has been corrected before changing the SPI back to master

mode.

12.4 SPI Registers and Control Bits

The SPI has five 8-bit registers to select SPI options, control baud rate, report SPI status, and for

transmit/receive data.

Refer to the direct-page register summary in the Memory section of this data sheet for the absolute address

assignments for all SPI registers. This section refers to registers and control bits only by their names, and

a Motorola-provided equate or header file is used to translate these names into the appropriate absolute

addresses.

12.4.1 SPI Control Register 1 (SPIC1)

This read/write register includes the SPI enable control, interrupt enables, and configuration options.

Figure 12-7 SPI Control Register 1 (SPIC1)

SPIE — SPI Interrupt Enable (for SPRF and MODF)

This is the interrupt enable for SPI receive buffer full (SPRF) and mode fault (MODF) events.

1 = When SPRF or MODF is 1, request a hardware interrupt.

0 = Interrupts from SPRF and MODF inhibited (use polling).

SPE — SPI System Enable

Disabling the SPI halts any transfer that is in progress, clears data buffers, and initializes internal state

machines. SPRF is cleared and SPTEF is set to indicate the SPI transmit data buffer is empty.

1 = SPI system enabled.

0 = SPI system inactive.

Bit 7

654321

Bit 0

Read:

SPIE

SPE

SPTIE

MSTR

CPOL

CPHA

SSOE

LSBFE

Write:

Reset:

00000100

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