HCS08 datasheet(196/290 Pages) MOTOROLA

196 / 290 page

Serial Peripheral Interface (SPI) Module

MC9S08GB/GT

196

MOTOROLA

In the case of a receive overrun, the new data is lost because the receive buffer still held the previous

character and was not ready to accept the new data. There is no indication for such an overrun condition

so the application system designer must ensure that previous data has been read from the receive buffer

before a new transfer is initiated.

12.3.1 SPI Clock Formats

To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI

system has a clock polarity (CPOL) bit and a clock phase (CPHA) control bit to select one of four clock

formats for data transfers. CPOL selectively inserts an inverter in series with the clock. CPHA chooses

between two different clock phase relationships between the clock and data.

Figure 12-5 shows the clock formats when CPHA = 1. At the top of the figure, the eight bit times are

shown for reference with bit 1 starting at the first SPSCK edge and bit 8 ending one-half SPSCK cycle

after the sixteenth SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits

depending on the setting in LSBFE. Both variations of SPSCK polarity are shown, but only one of these

waveforms applies for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform

applies to the MOSI input of a slave or the MISO input of a master. The MOSI waveform applies to the

MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS

OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The

master SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back

high at the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input

of a slave.

HCS08 bảng dữ liệu(PDF) 196 Page - Motorola, Inc