HCS08 datasheet(195/290 Pages) MOTOROLA

195 / 290 page

Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

195

MC9S08GB/GT

12.2.3 SPI Baud Rate Generation

As shown in Figure 12-4, the clock source for the SPI baud rate generator is the bus clock. The three

prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate

select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256

to get the internal SPI master mode bit-rate clock.

Figure 12-4 SPI Baud Rate Generation

12.3 Functional Description

An SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPTEF = 1) and then

writing a byte of data to the SPI data register (SPID) in the master SPI device. When the SPI shift register

is available, this byte of data is moved from the transmit data buffer to the shifter, SPTEF is cleared to

indicate there is room in the buffer to queue another transmit character if desired, and the SPI serial transfer

starts.

During the SPI transfer, data is sampled (read) on the MISO pin at one SPSCK edge and shifted, changing

the bit value on the MOSI pin, one-half SPSCK cycle later. After eight SPSCK cycles, the data that was

in the shift register of the master has been shifted out the MOSI pin to the slave while eight bits of data

were shifted in the MISO pin into the master’s shift register. At the end of this transfer, the received data

byte is moved from the shifter into the receive data buffer and SPRF is set to indicate the data can be read

by reading SPID. If another byte of data is waiting in the transmit buffer at the end of a transfer, it is moved

into the shifter, SPTEF is set, and a new transfer is started.

Normally, SPI data is transferred most significant bit (MSB) first. If the least significant bit first enable

(LSBFE) bit is set, SPI data is shifted LSB first.

When the SPI is configured as a slave, its SS pin must be driven low before a transfer starts and SS must

stay low throughout the transfer. If a clock format where CPHA = 0 is selected, SS must be driven to a

logic 1 between successive transfers. If CPHA = 1, SS may remain low between successive transfers. See

12.3.1 SPI Clock Formats for more details.

Because the transmitter and receiver are double buffered, a second byte, in addition to the byte currently

being shifted out, can be queued into the transmit data buffer, and a previously received character can be

in the receive data buffer while a new character is being shifted in. The SPTEF flag indicates when the

transmit buffer has room for a new character. The SPRF flag indicates when a received character is

available in the receive data buffer. The received character must be read out of the receive buffer (read

SPID) before the next transfer is finished or a receive overrun error results.

DIVIDE BY

2, 4, 8, 16, 32, 64, 128, or 256

DIVIDE BY

1, 2, 3, 4, 5, 6, 7, or 8

PRESCALER

CLOCK RATE DIVIDER

SPPR2:SPPR1:SPPR0

SPR2:SPR1:SPR0

BUS CLOCK

MASTER

SPI

BIT RATE

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