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HCS08 bảng dữ liệu(PDF) 205 Page - Motorola, Inc

tên linh kiện HCS08
Giải thích chi tiết về linh kiện  Microcontrollers
PDF  290 Pages
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nhà sản xuất  MOTOROLA [Motorola, Inc]
Trang chủ  http://www.freescale.com
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HCS08 bảng dữ liệu(HTML) 205 Page - Motorola, Inc

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Data Sheet — MC9S08GB60/D V1.5
MOTOROLA
205
MC9S08GB/GT
SPTEF — SPI Transmit Buffer Empty Flag
This bit is set when there is room in the transmit data buffer. It is cleared by reading SPIS with SPTEF
set, followed by writing a data value to the transmit buffer at SPID. SPIS must be read with SPTEF = 1
before writing data to SPID or the SPID write will be ignored. SPTEF generates an SPTEF CPU
interrupt request if the SPTIE bit in the SPIC1 is also set. SPTEF is automatically set when a data byte
transfers from the transmit buffer into the transmit shift register. For an idle SPI (no data in the transmit
buffer or the shift register and no transfer in progress), data written to SPID is transferred to the shifter
almost immediately so SPTEF is set within two bus cycles allowing a second 8-bit data value to be
queued into the transmit buffer. After completion of the transfer of the value in the shift register, the
queued value from the transmit buffer will automatically move to the shifter and SPTEF will be cleared
to indicate there is room for new data in the transmit buffer. If no new data is waiting in the transmit
buffer, SPTEF simply remains set and no data moves from the buffer to the shifter.
1 = SPI transmit buffer empty.
0 = SPI transmit buffer not empty.
MODF — Master Mode Fault Flag
MODF is set if the SPI is configured as a master and the slave select input goes low, indicating some
other SPI device is also configured as a master. The SS pin acts as a mode fault error input only when
MSTR = 1, MODFEN = 1, and SSOE = 0; otherwise, MODF will never be set. MODF is cleared by
reading MODF while it is 1, then writing to SPI control register 1 (SPIC1).
1 = Mode fault error detected.
0 = No mode fault error.
12.4.5 SPI Data Register (SPID)
Figure 12-11 SPI Data Register (SPID)
Reads of this register return the data read from the receive data buffer. Writes to this register write data
to the transmit data buffer. When the SPI is configured as a master, writing data to the transmit data
buffer initiates an SPI transfer.
Data should not be written to the transmit data buffer unless the SPI transmit buffer empty flag
(SPTEF) is set, indicating there is room in the transmit buffer to queue a new transmit byte.
Data may be read from SPID any time after SPRF is set and before another transfer is finished. Failure
to read the data out of the receive data buffer before a new transfer ends causes a receive overrun
condition and the data from the new transfer is lost.
Bit 7
654321
Bit 0
Read:
Bit 7
654321
Bit 0
Write:
Reset:
00000000



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