HCS08 datasheet(183/290 Pages) MOTOROLA

183 / 290 page

Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

183

MC9S08GB/GT

LOOPS — Loop Mode Select

Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS = 1, the

transmitter output is internally connected to the receiver input.

1 = Loop mode or single-wire mode where transmitter outputs are internally connected to receiver

input. (See RSRC bit.) RxD pin is not used by SCI.

0 = Normal operation — RxD and TxD use separate pins.

SCISWAI — SCI Stops in Wait Mode

1 = SCI clocks freeze while CPU is in wait mode.

0 = SCI clocks continue to run in wait mode so the SCI can be the source of an interrupt that wakes

up the CPU.

RSRC — Receiver Source Select

This bit has no meaning or effect unless the LOOPS bit is set to 1. When LOOPS = 1, the receiver input

is internally connected to the TxD pin and RSRC determines whether this connection is also connected

to the transmitter output.

1 = Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver

input.

0 = Provided LOOPS = 1, RSRC = 0 selects internal loop back mode and the SCI does not use the

RxD or TxD pins.

M — 9-Bit or 8-Bit Mode Select

1 = Receiver and transmitter use 9-bit data characters

start + 8 data bits (LSB first) + 9th data bit + stop.

0 = Normal — start + 8 data bits (LSB first) + stop.

WAKE — Receiver Wakeup Method Select

Refer to 11.6.3 Receiver Wakeup Operation for more information.

1 = Address-mark wakeup.

0 = Idle-line wakeup.

ILT — Idle Line Type Select

Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count toward

the 10 or 11 bit times of the logic high level by the idle line detection logic. Refer to 11.6.3.1 Idle-Line

Wakeup for more information.

1 = Idle character bit count starts after stop bit.

0 = Idle character bit count starts after start bit.

PE — Parity Enable

Enables hardware parity generation and checking. When parity is enabled, the most significant bit

(MSB) of the data character (eighth or ninth data bit) is treated as the parity bit.

1 = Parity enabled.

0 = No hardware parity generation or checking.

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