HCS08 datasheet(179/290 Pages) MOTOROLA

179 / 290 page

Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

179

MC9S08GB/GT

11.6.3 Receiver Wakeup Operation

Receiver wakeup is a hardware mechanism that allows an SCI receiver to ignore the characters in a

message that is intended for a different SCI receiver. In such a system, all receivers evaluate the first

character(s) of each message, and as soon as they determine the message is intended for a different

receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCIxC2. When RWU = 1, it

inhibits setting of the status flags associated with the receiver, thus eliminating the software overhead for

handling the unimportant message characters. At the end of a message, or at the beginning of the next

message, all receivers automatically force RWU to 0 so all receivers wake up in time to look at the first

character(s) of the next message.

11.6.3.1 Idle-Line Wakeup

When WAKE = 0, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared

automatically when the receiver detects a full character time of the idle-line level. The M control bit selects

8-bit or 9-bit data mode which determines how many bit times of idle are needed to constitute a full

character time (10 or 11 bit times because of the start and stop bits). The idle-line type (ILT) control bit

selects one of two ways to detect an idle line. When ILT = 0, the idle bit counter starts after the start bit so

the stop bit and any logic 1s at the end of a character count toward the full character time of idle. When

ILT = 1, the idle bit counter doesn’t start until after a stop bit time, so the idle detection is not affected by

the data in the last character of the previous message.

11.6.3.2 Address-Mark Wakeup

When WAKE = 1, the receiver is configured for address-mark wakeup. In this mode, RWU is cleared

automatically when the receiver detects a logic 1 in the most significant bit of a received character (eighth

bit in M = 0 mode and ninth bit in M = 1 mode).

11.7 Interrupts and Status Flags

The SCI system has three separate interrupt vectors to reduce the amount of software needed to isolate the

cause of the interrupt. One interrupt vector is associated with the transmitter for TDRE and TC events.

Another interrupt vector is associated with the receiver for RDRF and IDLE events, and a third vector is

used for OR, NF, FE, and PF error conditions. Each of these eight interrupt sources can be separately

masked by local interrupt enable masks. The flags can still be polled by software when the local masks are

cleared to disable generation of hardware interrupt requests.

The SCI transmitter has two status flags that optionally can generate hardware interrupt requests. Transmit

data register empty (TDRE) indicates when there is room in the transmit data buffer to write another

transmit character to SCIxD. If the transmit interrupt enable (TIE) bit is set, a hardware interrupt will be

requested whenever TDRE = 1. Transmit complete (TC) indicates that the transmitter is finished

transmitting all data, preamble, and break characters and is idle with TxD high. This flag is often used in

systems with modems to determine when it is safe to turn off the modem. If the transmit complete interrupt

enable (TCIE) bit is set, a hardware interrupt will be requested whenever TC = 1. Instead of hardware

interrupts, software polling may be used to monitor the TDRE and TC status flags if the corresponding

TIE or TCIE local interrupt masks are 0s.

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