HCS08 datasheet(178/290 Pages) MOTOROLA

178 / 290 page

Serial Communications Interface (SCI) Module

MC9S08GB/GT

178

MOTOROLA

After receiving the stop bit into the receive shifter, and provided the receive data register is not already

full, the data character is transferred to the receive data register and the receive data register full (RDRF)

status flag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the

overrun (OR) status flag is set and the new data is lost. Because the SCI receiver is double buffered, the

program has one full character time after RDRF is set before the data in the receive data buffer must be

read to avoid a receiver overrun.

When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive

data register by reading SCIxD. The RDRF flag is cleared automatically by a 2-step sequence which is

normally satisfied in the course of the user’s program that handles receive data. Refer to 11.7 Interrupts

and Status Flags for more details about flag clearing.

11.6.2 Data Sampling Technique

The SCI receiver uses a 16

× baud rate clock for sampling. The receiver starts by taking logic level samples

at 16 times the baud rate to search for a falling edge on the RxD serial data input pin. A falling edge is

defined as a logic 0 sample after three consecutive logic 1 samples. The 16

× baud rate clock is used to

divide the bit time into 16 segments labeled RT1 through RT16. Once a falling edge is located, three more

samples are taken at RT3, RT5, and RT7 to make sure this was a real start bit and not just noise. If at least

two of these three samples are 0, the receiver assumes it is synchronized to a receive character.

The receiver then samples each bit time, including the start and stop bits, at RT8, RT9, and RT10 to

determine the logic level for that bit. The logic level is interpreted to be that of the majority of the samples

taken during the bit time. In the case of the start bit, the bit is assumed to be 0 if at least two of the samples

at RT3, RT5, and RT7 are 0 even if one or all of the samples taken at RT8, RT9, and RT10 are 1s. If any

sample in any bit time (including the start and stop bits) in a character frame fails to agree with the logic

level for that bit, the noise flag (NF) will be set when the received character is transferred to the receive

data buffer.

The falling edge detection logic continuously looks for falling edges, and if an edge is detected, the sample

clock is resynchronized to bit times. This improves the reliability of the receiver in the presence of noise

or mismatched baud rates. It does not improve worst case analysis because some characters do not have

any extra falling edges anywhere in the character frame.

In the case of a framing error, provided the received character was not a break character, the sampling logic

that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected

almost immediately.

In the case of a framing error, the receiver is inhibited from receiving any new characters until the framing

error flag is cleared. The receive shift register continues to function, but a complete character cannot

transfer to the receive data buffer if FE is still set.

HCS08 bảng dữ liệu(PDF) 178 Page - Motorola, Inc