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HCS08 bảng dữ liệu(PDF) 180 Page - Motorola, Inc

tên linh kiện HCS08
Giải thích chi tiết về linh kiện  Microcontrollers
PDF  290 Pages
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nhà sản xuất  MOTOROLA [Motorola, Inc]
Trang chủ  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

HCS08 bảng dữ liệu(HTML) 180 Page - Motorola, Inc

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Serial Communications Interface (SCI) Module
MC9S08GB/GT
180
MOTOROLA
When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive
data register by reading SCIxD. The RDRF flag is cleared by reading SCIxS1 while RDRF = 1 and then
reading SCIxD.
When polling is used, this sequence is naturally satisfied in the normal course of the user program. If
hardware interrupts are used, SCIxS1 must be read in the interrupt service routine (ISR). Normally, this is
done in the ISR anyway to check for receive errors, so the sequence is automatically satisfied.
The IDLE status flag includes logic which prevents it from getting set repeatedly when the RxD line
remains idle for an extended period of time. IDLE is cleared by reading SCIxS1 while IDLE = 1 and then
reading SCIxD. Once IDLE has been cleared, it cannot become set again until the receiver has received at
least one new character and has set RDRF.
If the associated error was detected in the received character that caused RDRF to be set, the error flags
— noise flag (NF), framing error (FE), and parity error flag (PF) — get set at the same time as RDRF.
These flags are not set in overrun cases.
If RDRF was already set when a new character is ready to be transferred from the receive shifter to the
receive data buffer, the overrun (OR) flag gets set instead and the data and any associated NF, FE, or PF
condition is lost.
11.8 Additional SCI Functions
The following sections describe additional SCI functions.
11.8.1 8- and 9-Bit Data Modes
The SCI system (transmitter and receiver) can be configured to operate in 9-bit data mode by setting the
M control bit in SCIxC1. In 9-bit mode, there is a ninth data bit to the left of the MSB of the SCI data
register. For the transmit data buffer, this bit is stored in T8 in SCIxC3. For the receiver, the ninth bit is
held in R8 in SCIxC3.
For coherent writes to the transmit data buffer, write to the T8 bit before writing to SCIxD. For coherent
reads of the receive data buffer, read R8 before reading SCIxD because reading or writing SCIxD is the
final step in automatic clearing mechanisms for SCI flags.
If the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character,
it is not necessary to write to T8 again. When data is transferred from the transmit data buffer to the
transmit shifter, the value in T8 is copied at the same time data is transferred from SCIxD to the shifter.
Nine-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity
in the ninth bit. Or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit.
In custom protocols, the ninth bit can also serve as a software-controlled marker.



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