HCS08 datasheet(213/316 Pages) NXP

213 / 316 page

Serial Communications Interface (S08SCIV4)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

213

Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity

that is in progress must first be completed. This includes data characters in progress, queued idle

characters, and queued break characters.

14.3.2.1

Send Break and Queued Idle

The SBK control bit in SCIC2 is used to send break characters which were originally used to gain the

attention of old teletype receivers. Break characters are a full character time of logic 0 (10 bit times

including the start and stop bits). A longer break of 13 bit times can be enabled by setting BRK13 = 1.

Normally, a program would wait for TDRE to become set to indicate the last character of a message has

moved to the transmit shifter, then write 1 and then write 0 to the SBK bit. This action queues a break

character to be sent as soon as the shifter is available. If SBK is still 1 when the queued break moves into

the shifter (synchronized to the baud rate clock), an additional break character is queued. If the receiving

device is another Freescale Semiconductor SCI, the break characters will be received as 0s in all eight data

bits and a framing error (FE = 1) occurs.

When idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake

up any sleeping receivers. Normally, a program would wait for TDRE to become set to indicate the last

character of a message has moved to the transmit shifter, then write 0 and then write 1 to the TE bit. This

action queues an idle character to be sent as soon as the shifter is available. As long as the character in the

shifter does not finish while TE = 0, the SCI transmitter never actually releases control of the TxD pin. If

there is a possibility of the shifter finishing while TE = 0, set the general-purpose I/O controls so the pin

that is shared with TxD is an output driving a logic 1. This ensures that the TxD line will look like a normal

idle line even if the SCI loses control of the port pin between writing 0 and then 1 to TE.

The length of the break character is affected by the BRK13 and M bits as shown below.

14.3.3

Receiver Functional Description

In this section, the receiver block diagram (Figure 14-3) is used as a guide for the overall receiver

functional description. Next, the data sampling technique used to reconstruct receiver data is described in

more detail. Finally, two variations of the receiver wakeup function are explained.

The receiver input is inverted by setting RXINV = 1. The receiver is enabled by setting the RE bit in

SCIC2. Character frames consist of a start bit of logic 0, eight (or nine) data bits (LSB first), and a stop bit

of logic 1. For information about 9-bit data mode, refer to Section 14.3.5.1, “8- and 9-Bit Data Modes.”

For the remainder of this discussion, we assume the SCI is configured for normal 8-bit data mode.

After receiving the stop bit into the receive shifter, and provided the receive data register is not already

full, the data character is transferred to the receive data register and the receive data register full (RDRF)

Table 14-8. Break Character Length

BRK13

Break Character Length

10 bit times

11 bit times

13 bit times

14 bit times

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