HCS08 datasheet(216/316 Pages) NXP

216 / 316 page

Serial Communications Interface (S08SCIV4)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

216

Freescale Semiconductor

Instead of hardware interrupts, software polling may be used to monitor the TDRE and TC status flags if

the corresponding TIE or TCIE local interrupt masks are 0s.

When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive

data register by reading SCID. The RDRF flag is cleared by reading SCIS1 while RDRF = 1 and then

reading SCID.

When polling is used, this sequence is naturally satisfied in the normal course of the user program. If

hardware interrupts are used, SCIS1 must be read in the interrupt service routine (ISR). Normally, this is

done in the ISR anyway to check for receive errors, so the sequence is automatically satisfied.

The IDLE status flag includes logic that prevents it from getting set repeatedly when the RxD line remains

idle for an extended period of time. IDLE is cleared by reading SCIS1 while IDLE = 1 and then reading

SCID. After IDLE has been cleared, it cannot become set again until the receiver has received at least one

new character and has set RDRF.

If the associated error was detected in the received character that caused RDRF to be set, the error flags

— noise flag (NF), framing error (FE), and parity error flag (PF) — get set at the same time as RDRF.

These flags are not set in overrun cases.

If RDRF was already set when a new character is ready to be transferred from the receive shifter to the

receive data buffer, the overrun (OR) flag gets set instead the data along with any associated NF, FE, or PF

condition is lost.

At any time, an active edge on the RxD serial data input pin causes the RXEDGIF flag to set. The

RXEDGIF flag is cleared by writing a “1” to it. This function does depend on the receiver being enabled

(RE = 1).

14.3.5

Additional SCI Functions

The following sections describe additional SCI functions.

14.3.5.1

8- and 9-Bit Data Modes

The SCI system (transmitter and receiver) can be configured to operate in 9-bit data mode by setting the

M control bit in SCIC1. In 9-bit mode, there is a ninth data bit to the left of the MSB of the SCI data

in R8 in SCIC3.

For coherent writes to the transmit data buffer, write to the T8 bit before writing to SCID.

If the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character,

it is not necessary to write to T8 again. When data is transferred from the transmit data buffer to the

transmit shifter, the value in T8 is copied at the same time data is transferred from SCID to the shifter.

9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the

ninth bit. Or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. In

custom protocols, the ninth bit can also serve as a software-controlled marker.

HCS08 bảng dữ liệu(PDF) 216 Page - NXP Semiconductors