HCS08 datasheet(215/316 Pages) NXP

215 / 316 page

Serial Communications Interface (S08SCIV4)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

215

characters. At the end of a message, or at the beginning of the next message, all receivers automatically

force RWU to 0 so all receivers wake up in time to look at the first character(s) of the next message.

14.3.3.2.1

Idle-Line Wakeup

When WAKE = 0, the receiver is configured for idle-line wakeup. In this mode, RWU is cleared

automatically when the receiver detects a full character time of the idle-line level. The M control bit selects

8-bit or 9-bit data mode that determines how many bit times of idle are needed to constitute a full character

time (10 or 11 bit times because of the start and stop bits).

When RWU is one and RWUID is zero, the idle condition that wakes up the receiver does not set the IDLE

flag. The receiver wakes up and waits for the first data character of the next message which will set the

RDRF flag and generate an interrupt if enabled. When RWUID is one, any idle condition sets the IDLE

flag and generates an interrupt if enabled, regardless of whether RWU is zero or one.

The idle-line type (ILT) control bit selects one of two ways to detect an idle line. When ILT = 0, the idle

bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward

the full character time of idle. When ILT = 1, the idle bit counter does not start until after a stop bit time,

so the idle detection is not affected by the data in the last character of the previous message.

14.3.3.2.2

Address-Mark Wakeup

When WAKE = 1, the receiver is configured for address-mark wakeup. In this mode, RWU is cleared

automatically when the receiver detects a logic 1 in the most significant bit of a received character (eighth

bit in M = 0 mode and ninth bit in M = 1 mode).

Address-mark wakeup allows messages to contain idle characters but requires that the MSB be reserved

for use in address frames. The logic 1 MSB of an address frame clears the RWU bit before the stop bit is

received and sets the RDRF flag. In this case the character with the MSB set is received even though the

receiver was sleeping during most of this character time.

14.3.4

Interrupts and Status Flags

The SCI system has three separate interrupt vectors to reduce the amount of software needed to isolate the

cause of the interrupt. One interrupt vector is associated with the transmitter for TDRE and TC events.

Another interrupt vector is associated with the receiver for RDRF, IDLE, RXEDGIF and LBKDIF events,

and a third vector is used for OR, NF, FE, and PF error conditions. Each of these ten interrupt sources can

be separately masked by local interrupt enable masks. The flags can still be polled by software when the

local masks are cleared to disable generation of hardware interrupt requests.

The SCI transmitter has two status flags that optionally can generate hardware interrupt requests. Transmit

data register empty (TDRE) indicates when there is room in the transmit data buffer to write another

transmit character to SCID. If the transmit interrupt enable (TIE) bit is set, a hardware interrupt will be

requested whenever TDRE = 1. Transmit complete (TC) indicates that the transmitter is finished

transmitting all data, preamble, and break characters and is idle with TxD at the inactive level. This flag is

often used in systems with modems to determine when it is safe to turn off the modem. If the transmit

complete interrupt enable (TCIE) bit is set, a hardware interrupt will be requested whenever TC = 1.

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