HCS08 datasheet(210/316 Pages) NXP

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Serial Communications Interface (S08SCIV4)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

210

Freescale Semiconductor

When using an internal oscillator in a LIN system, it is necessary to raise the break detection threshold by

one bit time. Under the worst case timing conditions allowed in LIN, it is possible that a 0x00 data

character can appear to be 10.26 bit times long at a slave which is running 14% faster than the master. This

would trigger normal break detection circuitry which is designed to detect a 10 bit break symbol. When

the LBKDE bit is set, framing errors are inhibited and the break detection threshold changes from 10 bits

to 11 bits, preventing false detection of a 0x00 data character as a LIN break symbol.

14.2.6

SCI Control Register 3 (SCIC3)

LBKDE

LIN Break Detection Enable— LBKDE is used to select a longer break character detection length. While LBKDE

is set, framing error (FE) and receive data register full (RDRF) flags are prevented from setting.

0 Break character is detected at length of 10 bit times (11 if M = 1).

1 Break character is detected at length of 11 bit times (12 if M = 1).

RAF

Receiver Active Flag — RAF is set when the SCI receiver detects the beginning of a valid start bit, and RAF is

cleared automatically when the receiver detects an idle line. This status flag can be used to check whether an

SCI character is being received before instructing the MCU to go to stop mode.

0 SCI receiver idle waiting for a start bit.

1 SCI receiver active (RxD input not idle).

1 Setting RXINV inverts the RxD input for all cases: data bits, start and stop bits, break, and idle.

321

RR8

TXDIR

TXINV

ORIE

NEIE

FEIE

PEIE

Reset

000

= Unimplemented or Reserved

Figure 14-10. SCI Control Register 3 (SCIC3)

Table 14-7. SCIC3 Field Descriptions

Field

Description

Ninth Data Bit for Receiver — When the SCI is configured for 9-bit data (M = 1), R8 can be thought of as a ninth

receive data bit to the left of the MSB of the buffered data in the SCID register. When reading 9-bit data, read R8

before reading SCID because reading SCID completes automatic flag clearing sequences which could allow R8

and SCID to be overwritten with new data.

Ninth Data Bit for Transmitter — When the SCI is configured for 9-bit data (M = 1), T8 may be thought of as a

ninth transmit data bit to the left of the MSB of the data in the SCID register. When writing 9-bit data, the entire

9-bit value is transferred to the SCI shift register after SCID is written so T8 should be written (if it needs to change

from its previous value) before SCID is written. If T8 does not need to change in the new value (such as when it

is used to generate mark or space parity), it need not be written each time SCID is written.

TXDIR

TxD Pin Direction in Single-Wire Mode — When the SCI is configured for single-wire half-duplex operation

(LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin.

0 TxD pin is an input in single-wire mode.

1 TxD pin is an output in single-wire mode.

Table 14-6. SCIS2 Field Descriptions (continued)

Field

Description

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