HCS08 datasheet(153/316 Pages) NXP

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Internal Clock Source (S08ICSV2)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

153

10.3.2

ICS Control Register 2 (ICSC2)

432

BDIV

RANGE

HGO

EREFS

ERCLKEN

EREFSTEN

Reset:

000

Figure 10-4. ICS Control Register 2 (ICSC2)

Table 10-3. ICS Control Register 2 Field Descriptions

Field

Description

7:6

BDIV

Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits. This

controls the bus frequency.

Encoding 0 — Divides selected clock by 1

Encoding 1 — Divides selected clock by 2 (reset default)

Encoding 2 — Divides selected clock by 4

Encoding 3 — Divides selected clock by 8

RANGE

Frequency Range Select — Selects the frequency range for the external oscillator.

1 High frequency range selected for the external oscillator

0 Low frequency range selected for the external oscillator

HGO

High Gain Oscillator Select — The HGO bit controls the external oscillator mode of operation.

1 Configure external oscillator for high gain operation

0 Configure external oscillator for low power operation

Low Power Select — The LP bit controls whether the FLL is disabled in FLL bypassed modes.

1 FLL is disabled in bypass modes unless BDM is active

0 FLL is not disabled in bypass mode

EREFS

External Reference Select — The EREFS bit selects the source for the external reference clock.

1 Oscillator requested

0 External Clock Source requested

ERCLKEN

External Reference Enable — The ERCLKEN bit enables the external reference clock for use as ICSERCLK.

1ICSERCLK active

0 ICSERCLK inactive

EREFSTEN

External Reference Stop Enable — The EREFSTEN bit controls whether or not the external reference clock

remains enabled when the ICS enters stop mode.

1 External reference clock stays enabled in stop if ERCLKEN is set or if ICS is in FEE, FBE, or FBELP mode

before entering stop

0 External reference clock is disabled in stop

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