HCS08 datasheet(155/316 Pages) NXP

155 / 316 page

Internal Clock Source (S08ICSV2)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

155

10.4

Functional Description

10.4.1

Operational Modes

Figure 10-7. Clock Switching Modes

The seven states of the ICS are shown as a state diagram and are described below. The arrows indicate the

allowed movements between the states.

10.4.1.1

FLL Engaged Internal (FEI)

FLL engaged internal (FEI) is the default mode of operation and is entered when all the following

conditions occur:

OSC Initialization — If the external reference clock is selected by ERCLKEN or by the ICS being in FEE, FBE,

or FBELP mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator

clock have completed. This bit is only cleared when either ERCLKEN or EREFS are cleared.

ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency.

Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount

possible.

Table 10-5. ICS Status and Control Register Field Descriptions (continued)

Field

Description

FLL Bypassed

Internal Low

Power(FBILP)

IREFS=1

CLKS=00

Entered from any state

when MCU enters stop

FLL Engaged

Internal (FEI)

FLL Bypassed

Internal (FBI)

FLL Bypassed

External (FBE)

FLL Engaged

External (FEE)

FLL Bypassed

External Low

Power(FBELP)

IREFS=0

CLKS=00

IREFS=0

CLKS=10

BDM Enabled

or LP =0

Returns to state that was active

before MCU entered stop, unless

RESET occurs while in stop.

IREFS=0

CLKS=10

BDM Disabled

and LP=1

IREFS=1

CLKS=01

BDM Enabled

or LP=0

IREFS=1

CLKS=01

BDM Disabled

and LP=1

Stop

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