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HCS08 bảng dữ liệu(PDF) 154 Page - NXP Semiconductors |
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HCS08 bảng dữ liệu(HTML) 154 Page - NXP Semiconductors |
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154 / 316 page ![]() Internal Clock Source (S08ICSV2) MC9S08SG8 MCU Series Data Sheet, Rev. 8 154 Freescale Semiconductor 10.3.3 ICS Trim Register (ICSTRM) 10.3.4 ICS Status and Control (ICSSC) 7 6 5 432 1 0 R TRIM W POR: 1 0 0 0 0 0 0 0 Reset: U U U UUU U U Figure 10-5. ICS Trim Register (ICSTRM) Table 10-4. ICS Trim Register Field Descriptions Field Description 7:0 TRIM ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0). Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period. An additional fine trim bit is available in ICSSC as the FTRIM bit. 7 6 5 432 1 0 R 0 0 0 IREFST CLKST OSCINIT FTRIM W POR: Reset: 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 U Figure 10-6. ICS Status and Control Register (ICSSC) Table 10-5. ICS Status and Control Register Field Descriptions Field Description 7:5 Reserved, should be cleared. 4 IREFST Internal Reference Status — The IREFST bit indicates the current source for the reference clock. The IREFST bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock domains. 0 Source of reference clock is external clock. 1 Source of reference clock is internal clock. 3-2 CLKST Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don’t update immediately after a write to the CLKS bits due to internal synchronization between clock domains. 00 Output of FLL is selected. 01 FLL Bypassed, Internal reference clock is selected. 10 FLL Bypassed, External reference clock is selected. 11 Reserved. |
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