HCS08 datasheet(278/374 Pages) NXP

278 / 374 page

Timer/PWM Module (S08TPMV3)

MC9S08JM60 Series Data Sheet, Rev. 5

278

Freescale Semiconductor

16.3

This section consists of register descriptions in address order. A typical MCU system may contain multiple

TPMs, and each TPM may have one to eight channels, so register names include placeholder characters to

identify which TPM and which channel is being referenced. For example, TPMxCnSC refers to timer

(TPM) x, channel n. TPM1C2SC would be the status and control register for channel 2 of timer 1.

16.3.1

TPM Status and Control Register (TPMxSC)

TPMxSC contains the overflow status flag and control bits used to configure the interrupt enable, TPM

configuration, clock source, and prescale factor. These controls relate to all channels within this timer

module.

RTOF

TOIE

CPWMS

CLKSB

CLKSA

PS2

PS1

PS0

Reset

Figure 16-7. TPM Status and Control Register (TPMxSC)

Table 16-2. TPMxSC Field Descriptions

Field

Description

TOF

Timer overflow flag. This read/write flag is set when the TPM counter resets to 0x0000 after reaching the modulo

value programmed in the TPM counter modulo registers. Clear TOF by reading the TPM status and control

sequence is complete, the sequence is reset so TOF would remain set after the clear sequence was completed

for the earlier TOF. This is done so a TOF interrupt request cannot be lost during the clearing sequence for a

previous TOF. Reset clears TOF. Writing a logic 1 to TOF has no effect.

0 TPM counter has not reached modulo value or overflow

1 TPM counter has overflowed

TOIE

Timer overflow interrupt enable. This read/write bit enables TPM overflow interrupts. If TOIE is set, an interrupt is

generated when TOF equals one. Reset clears TOIE.

0 TOF interrupts inhibited (use for software polling)

1 TOF interrupts enabled

CPWMS

Center-aligned PWM select. When present, this read/write bit selects CPWM operating mode. By default, the TPM

operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting

CPWMS reconfigures the TPM to operate in up/down counting mode for CPWM functions. Reset clears CPWMS.

0 All channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the

MSnB:MSnA control bits in each channel’s status and control register.

1 All channels operate in center-aligned PWM mode.

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