HCS08 datasheet(257/290 Pages) MOTOROLA

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Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

257

MC9S08GB/GT

15.5.3.8 Debug Trigger Register (DBGT)

This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hardwired

to 0s.

Figure 15-8 Debug Trigger Register (DBGT)

TRGSEL — Trigger Type

Controls whether the match outputs from comparators A and B are qualified with the opcode tracking

logic in the debug module. If TRGSEL is set, a match signal from comparator A or B must propagate

through the opcode tracking logic and a trigger event is only signalled to the FIFO logic if the opcode

at the match address is actually executed.

1 = Trigger if opcode at compare address is executed (tag).

0 = Trigger on access to compare address (force).

BEGIN — Begin/End Trigger Select

Controls whether the FIFO starts filling at a trigger or fills in a circular manner until a trigger ends the

capture of information. In event-only trigger modes, this bit is ignored and all debug runs are assumed

to be begin traces.

1 = Trigger initiates data storage (begin trace).

0 = Data stored in FIFO until trigger (end trace).

TRG3:TRG2:TRG1:TRG0 — Select Trigger Mode

Selects one of nine triggering modes

Bit 7

4321

Bit 0

Read:

TRGSEL

BEGIN

TRG3

TRG2

TRG1

TRG0

Write:

Reset:

00000

= Unimplemented or Reserved

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