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HCS08 bảng dữ liệu(PDF) 254 Page - Motorola, Inc

tên linh kiện HCS08
Giải thích chi tiết về linh kiện  Microcontrollers
PDF  290 Pages
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nhà sản xuất  MOTOROLA [Motorola, Inc]
Trang chủ  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

HCS08 bảng dữ liệu(HTML) 254 Page - Motorola, Inc

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Development Support
MC9S08GB/GT
254
MOTOROLA
Figure 15-6 System Background Debug Force Reset Register (SBDFR)
BDFR — Background Debug Force Reset
A serial active background mode command such as WRITE_BYTE may be used to allow an external
debug host to force a target system reset. Writing logic 1 to this bit forces an MCU reset. This bit
cannot be written from a user program.
15.5.3 DBG Registers and Control Bits
The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control
and status registers. These registers are located in the high register space of the normal memory map so
they are accessible to normal application programs. These registers are rarely if ever accessed by normal
user application programs with the possible exception of a ROM patching mechanism that uses the
breakpoint logic.
15.5.3.1 Debug Comparator A High Register (DBGCAH)
This register contains compare value bits for the high-order eight bits of comparator A. This register is
forced to $00 at reset and can be read at any time or written at any time unless ARM = 1.
15.5.3.2 Debug Comparator A Low Register (DBGCAL)
This register contains compare value bits for the low-order eight bits of comparator A. This register is
forced to $00 at reset and can be read at any time or written at any time unless ARM = 1.
15.5.3.3 Debug Comparator B High Register (DBGCBH)
This register contains compare value bits for the high-order eight bits of comparator B. This register is
forced to $00 at reset and can be read at any time or written at any time unless ARM = 1.
15.5.3.4 Debug Comparator B Low Register (DBGCBL)
This register contains compare value bits for the low-order eight bits of comparator B. This register is
forced to $00 at reset and can be read at any time or written at any time unless ARM = 1.
Bit 7
654321
Bit 0
Read:
00000000
Write:
BDFR(1)
NOTES:
1. BDFR is writable only through serial active background mode debug commands, not from user programs.
Reset:
00010000
= Unimplemented or Reserved



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