HCS08 datasheet(252/290 Pages) MOTOROLA

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MC9S08GB/GT

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Figure 15-5 BDC Status and Control Register (BDCSCR)

ENBDM — Enable BDM (Permit Active Background Mode)

Typically, this bit is written to 1 by the debug host shortly after the beginning of a debug session or

whenever the debug host resets the target and remains 1 until a normal reset clears it.

1 = BDM can be made active to allow active background mode commands.

0 = BDM cannot be made active (non-intrusive commands still allowed).

BDMACT — Background Mode Active Status

This is a read-only status bit.

1 = BDM active and waiting for serial commands.

0 = BDM not active (user application program running).

BKPTEN — BDC Breakpoint Enable

If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select) control bit and

BDCBKPT match register are ignored.

1 = BDC breakpoint enabled.

0 = BDC breakpoint disabled.

FTS — Force/Tag Select

When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the BDCBKPT

match register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register

causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction

queue, the CPU enters active background mode rather than executing the tagged opcode.

1 = Breakpoint match forces active background mode at next instruction boundary (address need

not be an opcode).

0 = Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute

that instruction.

CLKSW — Select Source for BDC Communications Clock

CLKSW defaults to 0 which selects the alternate BDC clock source.

1 = MCU bus clock.

0 = Alternate BDC clock source.

Bit 7

4321

Bit 0

Read:

ENBDM

BDMACT

BKPTEN

FTS

CLKSW

WSF

DVF

Write:

Normal Reset:

00000

Reset in Active BDM:

01000

= Unimplemented or Reserved

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