HCS08 datasheet(116/290 Pages) MOTOROLA

116 / 290 page

Central Processor Unit (CPU)

MC9S08GB/GT

116

MOTOROLA

The index register pair is then incremented (H:X = H:X + $0001) after the operand has been fetched. This

addressing mode is used only for the CBEQ instruction.

7.4.6.5 Indexed, 16-Bit Offset (IX2)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus a 16-bit offset

included in the instruction as the address of the operand needed to complete the instruction.

7.4.6.6 SP-Relative, 8-Bit Offset (SP1)

This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit

offset included in the instruction as the address of the operand needed to complete the instruction.

7.4.6.7 SP-Relative, 16-Bit Offset (SP2)

This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset

included in the instruction as the address of the operand needed to complete the instruction.

7.5 Special Operations

The CPU performs a few special operations which are similar to instructions but do not have opcodes like

other CPU instructions. In addition, a few instructions such as STOP and WAIT directly affect other MCU

circuitry. This section provides additional information about these operations.

7.5.1 Reset Sequence

Reset can be caused by a power-on-reset (POR) event, internal conditions such as the COP (computer

operating properly) watchdog, or by assertion of an external active-low reset pin. When a reset event

occurs, the CPU immediately stops whatever it is doing (the MCU does not wait for an instruction

boundary before responding to a reset event). For a more detailed discussion about how the MCU

recognizes resets and determines the source, refer to the Resets, Interrupts, and System Configuration

section.

The reset event is considered concluded when the sequence to determine whether the reset came from an

internal source is done and when the reset pin is no longer asserted. At the conclusion of a reset event, the

CPU performs a 6-cycle sequence to fetch the reset vector from $FFFE and $FFFF and to fill the

instruction queue in preparation for execution of the first program instruction.

7.5.2 Interrupt Sequence

When an interrupt is requested, the CPU completes the current instruction before responding to the

interrupt. At this point, the program counter is pointing at the start of the next instruction which is where

the CPU should return after servicing the interrupt. The CPU responds to an interrupt by performing the

same sequence of operations as for a software interrupt (SWI) instruction, except the address used for the

vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence

started.

HCS08 bảng dữ liệu(PDF) 116 Page - Motorola, Inc