HCS08 datasheet(115/290 Pages) MOTOROLA

115 / 290 page

Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

115

MC9S08GB/GT

7.4.3 Immediate Addressing Mode (IMM)

In immediate addressing mode, the operand needed to complete the instruction is included in the object

code immediately following the instruction opcode in memory. In the case of a 16-bit immediate operand,

the high-order byte is located in the next memory location after the opcode, and the low-order byte is

located in the next memory location after that.

7.4.4 Direct Addressing Mode (DIR)

In direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page

($0000–$00FF). During execution a 16-bit address is formed by concatenating an implied $00 for the

high-order half of the address and the direct address from the instruction to get the 16-bit address where

the desired operand is located. This is faster and more memory efficient than specifying a complete 16-bit

address for the operand.

7.4.5 Extended Addressing Mode (EXT)

In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of

program memory after the opcode (high byte first).

7.4.6 Indexed Addressing Mode

Indexed addressing mode has seven variations including five which use the 16-bit H:X index register pair

and two that use the stack pointer as the base reference.

7.4.6.1 Indexed, No Offset (IX)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of

the operand needed to complete the instruction.

7.4.6.2 Indexed, No Offset with Post Increment (IX+)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of

the operand needed to complete the instruction. The index register pair is then incremented

(H:X = H:X + $0001) after the operand has been fetched. This addressing mode is only used for MOV and

CBEQ instructions.

7.4.6.3 Indexed, 8-Bit Offset (IX1)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned

8-bit offset included in the instruction as the address of the operand needed to complete the instruction.

7.4.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned

8-bit offset included in the instruction as the address of the operand needed to complete the instruction.

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