HCS08 datasheet(113/290 Pages) MOTOROLA

113 / 290 page

Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

113

MC9S08GB/GT

Figure 7-2 Condition Code Register

V — Two’s Complement Overflow Flag

The CPU sets the overflow flag when a two’s complement overflow occurs. The signed branch

instructions BGT, BGE, BLE, and BLT use the overflow flag.

1 = Overflow

0 = No overflow

H — Half-Carry Flag

The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an

add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for

binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and

C condition code bits to automatically add a correction value to the result from a previous ADD or

ADC on BCD operands to correct the result to a valid BCD value.

1 = Carry between bits 3 and 4

0 = No carry between bits 3 and 4

I — Interrupt Mask Bit

When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled

when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set

automatically after the CPU registers are saved on the stack, but before the first instruction of the

interrupt service routine is executed.

1 = Interrupts disabled

0 = Interrupts enabled

Interrupts are not recognized at the instruction boundary after any instruction which clears I (CLI or

TAP). This ensures that the next instruction after a CLI or TAP will always be executed without the

possibility of an intervening interrupt, provided I was set.

N — Negative Flag

The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation

produces a negative result, setting bit 7 of the result. Simply loading or storing an 8-bit or 16-bit value

causes N to be set if the most significant bit of the loaded or stored value was 1.

1 = Negative result

0 = Non-negative result

CONDITION CODE REGISTER

CARRY

ZERO

NEGATIVE

INTERRUPT MASK

HALF-CARRY (FROM BIT 3)

TWO’S COMPLEMENT OVERFLOW

CCR

V1 1 H

N Z

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