HCS08 datasheet(110/290 Pages) MOTOROLA

110 / 290 page

Central Processor Unit (CPU)

MC9S08GB/GT

110

MOTOROLA

7.2 Features

Features of the HCS08 CPU include:

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Object code fully upward-compatible with M68HC05 and M68HC08 Families

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All registers and memory are mapped to a single 64-Kbyte address space

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16-bit stack pointer (any size stack anywhere in 64-Kbyte address space)

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16-bit index register (H:X) with powerful indexed addressing modes

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8-bit accumulator (A)

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Many instructions treat X as a second general-purpose 8-bit register

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Seven addressing modes:

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Inherent — Operands in internal registers

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Relative — 8-bit signed offset to branch destination

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Immediate — Operand in next object code byte(s)

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Direct — Operand in memory at $0000–$00FF

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Extended — Operand anywhere in 64-Kbyte address space

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Indexed relative to H:X — Five submodes including auto increment

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Indexed relative to SP — Improves C efficiency dramatically

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Memory-to-memory data move instructions with four address mode combinations

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Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on

the results of signed, unsigned, and binary-coded decimal (BCD) operations

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Efficient bit manipulation instructions

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Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions

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STOP and WAIT instructions to invoke low-power operating modes

7.3 Programmer’s Model and CPU Registers

Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map.

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