HCS08 datasheet(238/316 Pages) NXP

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Chapter 16 Timer Pulse-Width Modulator (S08TPMV3)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

238

Freescale Semiconductor

16.1.4

Migrating from TPMV1

In addition to Section 16.1.3, “TPMV3 Differences from Previous Versions,” keep in mind the following

considerations when migrating from a device that uses TPMV1.

•

You can write to the Channel Value register (TPMxCnV) when the timer is not in input capture

mode for TPMV2, not TPMV3.

In Center-Aligned PWM mode when (CLKSB:CLKSA not =

00), writes to TPMxCnVH:L registers4

Update the TPMxCnVH:L

registers with the value of

their write buffer after both

bytes are written and when

the TPM counter changes

from (TPMxMODH:L - 1) to

(TPMxMODH:L).

Note: If the TPM counter is a

free-running counter, then

this update is made when the

TPM counter changes from

0xFFFE to 0xFFFF.

Update after both bytes are

written and when the TPM

counter changes from

TPMxMODH:L to

(TPMxMODH:L - 1).

Center-Aligned PWM

When TPMxCnVH:L = TPMxMODH:L5

Produces 100% duty cycle.

Produces 0% duty cycle.

When TPMxCnVH:L = (TPMxMODH:L - 1)6

Produces a near 100% duty

cycle.

Produces 0% duty cycle.

TPMxCnVH:L is changed from 0x0000 to a non-zero value7

Waits for the start of a new

PWM period to begin using

the new duty cycle setting.

Changes the channel output at

the middle of the current PWM

period (when the count

reaches 0x0000).

TPMxCnVH:L is changed from a non-zero value to 0x00008

Finishes the current PWM

period using the old duty

cycle setting.

Finishes the current PWM

period using the new duty

cycle setting.

Write to TPMxMODH:L registers in BDM mode

In BDM mode, a write to TPMxSC register

Clears the write coherency

mechanism of

TPMxMODH:L registers.

Does not clear the write

coherency mechanism.

1 For more information, refer to Section 16.3.2, “TPM-Counter Registers (TPMxCNTH:TPMxCNTL) .” [SE110-TPM case 7]

2 For more information, refer to Section 16.3.5, “TPM Channel Value Registers (TPMxCnVH:TPMxCnVL).”

3 For more information, refer to Section 16.4.2.1, “Input Capture Mode .”

4 For more information, refer to Section 16.4.2.4, “Center-Aligned PWM Mode.”

5 For more information, refer to Section 16.4.2.4, “Center-Aligned PWM Mode.” [SE110-TPM case 1]

6 For more information, refer to Section 16.4.2.4, “Center-Aligned PWM Mode.” [SE110-TPM case 2]

7 For more information, refer to Section 16.4.2.4, “Center-Aligned PWM Mode.” [SE110-TPM case 3 and 5]

8 For more information, refer to Section 16.4.2.4, “Center-Aligned PWM Mode.” [SE110-TPM case 4]

Table 16-2. TPMV2 and TPMV3 Porting Considerations (continued)

Action

TPMV3

TPMV2

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