HCS08 datasheet(233/316 Pages) NXP

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Serial Peripheral Interface (S08SPIV3)

MC9S08SG8 MCU Series Data Sheet, Rev.8

Freescale Semiconductor

233

15.5.2

SPI Interrupts

There are three flag bits, two interrupt mask bits, and one interrupt vector associated with the SPI system.

The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode

fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI

transmit buffer empty flag (SPTEF). When one of the flag bits is set, and the associated interrupt mask bit

is set, a hardware interrupt request is sent to the CPU. If the interrupt mask bits are cleared, software can

poll the associated flag bits instead of using interrupts. The SPI interrupt service routine (ISR) should

check the flag bits to determine what event caused the interrupt. The service routine should also clear the

flag bit(s) before returning from the ISR (usually near the beginning of the ISR).

15.5.3

Mode Fault Detection

A mode fault occurs and the mode fault flag (MODF) becomes set when a master SPI device detects an

error on the SS pin (provided the SS pin is configured as the mode fault input signal). The SS pin is

configured to be the mode fault input signal when MSTR = 1, mode fault enable is set (MODFEN = 1),

and slave select output enable is clear (SSOE = 0).

The mode fault detection feature can be used in a system where more than one SPI device might become

a master at the same time. The error is detected when a master’s SS pin is low, indicating that some other

SPI device is trying to address this master as if it were a slave. This could indicate a harmful output driver

conflict, so the mode fault logic is designed to disable all SPI output drivers when such an error is detected.

When a mode fault is detected, MODF is set and MSTR is cleared to change the SPI configuration back

to slave mode. The output drivers on the SPSCK, MOSI, and MISO (if not bidirectional mode) are

disabled.

MODF is cleared by reading it while it is set, then writing to the SPI control register 1 (SPIC1). User

software should verify the error condition has been corrected before changing the SPI back to master

mode.

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