HCS08 datasheet(148/374 Pages) NXP

148 / 374 page

Analog-to-Digital Converter (S08ADC12V1)

MC9S08JM60 Series Data Sheet, Rev. 5

148

Freescale Semiconductor

10.4.1

Clock Select and Divide Control

One of four clock sources can be selected as the clock source for the ADC module. This clock source is

then divided by a configurable value to generate the input clock to the converter (ADCK). The clock is

selected from one of the following sources by means of the ADICLK bits.

•

The bus clock, which is equal to the frequency at which software is executed. This is the default

selection following reset.

•

The bus clock divided by two. For higher bus clock rates, this allows a maximum divide by 16 of

the bus clock.

•

ALTCLK, as defined for this MCU (See module section introduction).

•

The asynchronous clock (ADACK). This clock is generated from a clock source within the ADC

module. When selected as the clock source, this clock remains active while the MCU is in wait or

stop3 mode and allows conversions in these modes for lower noise operation.

Whichever clock is selected, its frequency must fall within the specified frequency range for ADCK. If the

available clocks are too slow, the ADC do not perform according to specifications. If the available clocks

are too fast, the clock must be divided to the appropriate frequency. This divider is specified by the ADIV

bits and can be divide-by 1, 2, 4, or 8.

10.4.2

Input Select and Pin Control

The pin control registers (APCTL3, APCTL2, and APCTL1) disable the I/O port control of the pins used

as analog inputs.When a pin control register bit is set, the following conditions are forced for the associated

MCU pin:

•

The output buffer is forced to its high impedance state.

•

The input buffer is disabled. A read of the I/O port returns a zero for any pin with its input buffer

disabled.

•

The pullup is disabled.

10.4.3

Hardware Trigger

The ADC module has a selectable asynchronous hardware conversion trigger, ADHWT, that is enabled

when the ADTRG bit is set. This source is not available on all MCUs. Consult the module introduction for

information on the ADHWT source specific to this MCU.

When ADHWT source is available and hardware trigger is enabled (ADTRG=1), a conversion is initiated

on the rising edge of ADHWT. If a conversion is in progress when a rising edge occurs, the rising edge is

ignored. In continuous convert configuration, only the initial rising edge to launch continuous conversions

is observed. The hardware trigger function operates in conjunction with any of the conversion modes and

configurations.

10.4.4

Conversion Control

Conversions can be performed in 12-bit mode, 10-bit mode, or 8-bit mode as determined by the MODE

bits. Conversions can be initiated by a software or hardware trigger. In addition, the ADC module can be

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