HCS08 datasheet(342/374 Pages) NXP

342 / 374 page

Development Support

MC9S08JM60 Series Data Sheet, Rev. 5

342

Freescale Semiconductor

18.4.3

DBG Registers and Control Bits

The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control

and status registers. These registers are located in the high register space of the normal memory map so

they are accessible to normal application programs. These registers are rarely if ever accessed by normal

user application programs with the possible exception of a ROM patching mechanism that uses the

breakpoint logic.

18.4.3.1

Debug Comparator A High Register (DBGCAH)

This register contains compare value bits for the high-order eight bits of comparator A. This register is

forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.

18.4.3.2

Debug Comparator A Low Register (DBGCAL)

This register contains compare value bits for the low-order eight bits of comparator A. This register is

forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.

18.4.3.3

Debug Comparator B High Register (DBGCBH)

This register contains compare value bits for the high-order eight bits of comparator B. This register is

forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.

18.4.3.4

Debug Comparator B Low Register (DBGCBL)

This register contains compare value bits for the low-order eight bits of comparator B. This register is

forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.

18.4.3.5

Debug FIFO High Register (DBGFH)

This register provides read-only access to the high-order eight bits of the FIFO. Writes to this register have

no meaning or effect. In the event-only trigger modes, the FIFO only stores data into the low-order byte

of each FIFO word, so this register is not used and will read 0x00.

Reading DBGFH does not cause the FIFO to shift to the next word. When reading 16-bit words out of the

FIFO, read DBGFH before reading DBGFL because reading DBGFL causes the FIFO to advance to the

next word of information.

Table 18-3. SBDFR Register Field Description

Field

Description

BDFR

Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE allows

an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot

be written from a user program.

HCS08 bảng dữ liệu(PDF) 342 Page - NXP Semiconductors

HCS08 bảng dữ liệu(HTML) 342 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL