HCS08 datasheet(339/374 Pages) NXP

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MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

339

18.3.6

Hardware Breakpoints

The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions

described in Section 18.3.5, “Trigger Modes,” to be used to generate a hardware breakpoint request to the

CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a

force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction

queue. If a tagged opcode reaches the end of the pipe, the CPU executes a BGND instruction to go to active

background mode rather than executing the tagged opcode. A force-type breakpoint causes the CPU to

finish the current instruction and then go to active background mode.

If the background mode has not been enabled (ENBDM = 1) by a serial WRITE_CONTROL command

through the BKGD pin, the CPU will execute an SWI instruction instead of going to active background

mode.

18.4

This section contains the descriptions of the BDC and DBG registers and control bits.

Refer to the high-page register summary in the device overview chapter of this data sheet for the absolute

address assignments for all DBG registers. This section refers to registers and control bits only by their

names. A Freescale-provided equate or header file is used to translate these names into the appropriate

absolute addresses.

18.4.1

BDC Registers and Control Bits

The BDC has two registers:

•

The BDC status and control register (BDCSCR) is an 8-bit register containing control and status

bits for the background debug controller.

•

The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match address.

These registers are accessed with dedicated serial BDC commands and are not located in the memory

space of the target MCU (so they do not have addresses and cannot be accessed by user programs).

Some of the bits in the BDCSCR have write limitations; otherwise, these registers may be read or written

at any time. For example, the ENBDM control bit may not be written while the MCU is in active

background mode. (This prevents the ambiguous condition of the control bit forbidding active background

mode while the MCU is already in active background mode.) Also, the four status bits (BDMACT, WS,

WSF, and DVF) are read-only status indicators and can never be written by the WRITE_CONTROL serial

BDC command. The clock switch (CLKSW) control bit may be read or written at any time.

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