HCS08 datasheet(215/290 Pages) MOTOROLA

215 / 290 page

Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

215

MC9S08GB/GT

13.5.2 IIC Frequency Divider Register (IICF)

Figure 13-6 IIC Frequency Divider Register (IICF)

MULT — IIC Multiplier Factor

The MULT bits define the multiplier factor mul. This factor is used along with the SCL divider to

generate the IIC baud rate. Table 13-2 provides the multiplier factor mul as defined by the MULT bits.

ICR — IIC Clock Rate

The ICR bits are used to prescale the bus clock for bit rate selection. These bits are used to define the

SCL divider and the SDA hold value. The SCL divider multiplied by the value provided by the MULT

IIC baud rate = bus speed (Hz)/(mul * SCL divider)

SDA hold time is the delay from the falling edge of the SCL (IIC clock) to the changing of SDA (IIC

data). The ICR is used to determine the SDA hold value.

SDA hold time = bus period (s) * SDA hold value

Table 13-3 provides the SCL divider and SDA hold values for corresponding values of the ICR. These

values can be used to set IIC baud rate and SDA hold time. For example:

Bus speed = 8 MHz

MULT is set to 01 (mul = 2)

Desired IIC baud rate = 100 kbps

IIC baud rate = bus speed (Hz)/(mul * SCL divider)

100000 = 8000000/(2*SCL divider)

SCL divider = 40

Table 13-3 shows that ICR must be set to 0B to provide an SCL divider of 40 and that this will result

in an SDA hold value of 9.

SDA hold time = bus period (s) * SDA hold value

SDA hold time = 1/8000000 * 9 = 1.125

µs

Bit 7

654321

Bit 0

Read:

MULT

ICR

Write:

Reset:

00000000

Table 13-2 Multiplier Factor

MULT

mul

Reserved

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