HCS08 datasheet(213/290 Pages) MOTOROLA

213 / 290 page

Data Sheet — MC9S08GB60/D V1.5

MOTOROLA

213

MC9S08GB/GT

13.2.1.8 Handshaking

The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold

the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces

the master clock into wait states until the slave releases the SCL line.

13.2.1.9 Clock Stretching

The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After

the master has driven SCL low the slave can drive SCL low for the required period and then release it. If

the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low

period is stretched.

13.3 Resets

The IIC is disabled after reset. The IIC cannot cause an MCU reset.

13.4 Interrupts

The IIC generates a single interrupt.

An interrupt from the IIC is generated when any of the events in Table 13-1 occur provided the IICIE bit

is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC

control register). The IICIF bit must be cleared by software by writing a one to it in the interrupt routine.

The user can determine the interrupt type by reading the status register.

13.4.1 Byte Transfer Interrupt

The TCF (transfer complete flag) bit is set at the falling edge of the 9th clock to indicate the completion

of byte transfer.

13.4.2 Address Detect Interrupt

When its own specific address (IIC address register) is matched with the calling address, the IAAS bit in

status register is set. The CPU is interrupted provided the IICIE is set. The CPU must check the SRW bit

and set its Tx mode accordingly.

Table 13-1 Interrupt Summary

Interrupt Source

Status

Flag

Local Enable

Complete 1-byte transfer

TCF

IICIF

IICIE

Match of received calling

address

IAAS

IICIF

IICIE

Arbitration Lost

ARBL

IICIF

IICIE

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