HCS08 datasheet(256/316 Pages) NXP

256 / 316 page

Timer/PWM Module (S08TPMV3)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

256

Freescale Semiconductor

In output compare mode, values are transferred to the corresponding timer channel registers only after both

8-bit halves of a 16-bit register have been written and according to the value of CLKSB:CLKSA bits, so:

•

If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written

•

If (CLKSB:CLKSA not = 0:0), the registers are updated at the next change of the TPM counter

(end of the prescaler counting) after the second byte is written.

The coherency sequence can be manually reset by writing to the channel status/control register

(TPMxCnSC).

An output compare event sets a flag bit (CHnF) which may optionally generate a CPU-interrupt request.

16.4.2.3

Edge-Aligned PWM Mode

This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS=0) and can

be used when other channels in the same TPM are configured for input capture or output compare

functions. The period of this PWM signal is determined by the value of the modulus register

(TPMxMODH:TPMxMODL) plus 1. The duty cycle is determined by the setting in the timer channel

ELSnA control bit. 0% and 100% duty cycle cases are possible.

The output compare value in the TPM channel registers determines the pulse width (duty cycle) of the

PWM signal (Figure 16-15). The time between the modulus overflow and the output compare is the pulse

width. If ELSnA=0, the counter overflow forces the PWM signal high, and the output compare forces the

PWM signal low. If ELSnA=1, the counter overflow forces the PWM signal low, and the output compare

forces the PWM signal high.

Figure 16-15. PWM Period and Pulse Width (ELSnA=0)

When the channel value register is set to 0x0000, the duty cycle is 0%. 100% duty cycle can be achieved

by setting the timer-channel register (TPMxCnVH:TPMxCnVL) to a value greater than the modulus

setting. This implies that the modulus setting must be less than 0xFFFF in order to get 100% duty cycle.

Because the TPM may be used in an 8-bit MCU, the settings in the timer channel registers are buffered to

ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers

TPMxCnVH and TPMxCnVL, actually write to buffer registers. In edge-aligned PWM mode, values are

transferred to the corresponding timer-channel registers according to the value of CLKSB:CLKSA bits, so:

•

If (CLKSB:CLKSA = 0:0), the registers are updated when the second byte is written

•

If (CLKSB:CLKSA not = 0:0), the registers are updated after the both bytes were written, and the

TPM counter changes from (TPMxMODH:TPMxMODL - 1) to (TPMxMODH:TPMxMODL). If

PERIOD

PULSE

WIDTH

OVERFLOW

OUTPUT

COMPARE

OUTPUT

COMPARE

OUTPUT

COMPARE

TPMxCHn

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