HCS08 datasheet(250/316 Pages) NXP

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Timer/PWM Module (S08TPMV3)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

250

Freescale Semiconductor

Reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first

counter overflow will occur.

16.3.4

TPM Channel n Status and Control Register (TPMxCnSC)

TPMxCnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt

enable, channel configuration, and pin function.

Bit 7

321

Bit 0

Reset

RCHnF

CHnIE

MSnB

MSnA

ELSnB

ELSnA

Reset

= Unimplemented or Reserved

Figure 16-12. TPM Channel n Status and Control Register (TPMxCnSC)

Table 16-8. TPMxCnSC Field Descriptions

Field

Description

CHnF

Channel n flag. When channel n is an input-capture channel, this read/write bit is set when an active edge occurs

on the channel n pin. When channel n is an output compare or edge-aligned/center-aligned PWM channel, CHnF

is set when the value in the TPM counter registers matches the value in the TPM channel n value registers. When

channel n is an edge-aligned/center-aligned PWM channel and the duty cycle is set to 0% or 100%, CHnF will not

be set even when the value in the TPM counter registers matches the value in the TPM channel n value registers.

A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF by

reading TPMxCnSC while CHnF is set and then writing a logic 0 to CHnF. If another interrupt request occurs

before the clearing sequence is complete, the sequence is reset so CHnF remains set after the clear sequence

completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost due to clearing a previous

CHnF.

Reset clears the CHnF bit. Writing a logic 1 to CHnF has no effect.

0 No input capture or output compare event occurred on channel n

1 Input capture or output compare event on channel n

CHnIE

Channel n interrupt enable. This read/write bit enables interrupts from channel n. Reset clears CHnIE.

0 Channel n interrupt requests disabled (use for software polling)

1 Channel n interrupt requests enabled

MSnB

Mode select B for TPM channel n. When CPWMS=0, MSnB=1 configures TPM channel n for edge-aligned PWM

mode. Refer to the summary of channel mode and setup controls in Table 16-9.

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