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HCS08 bảng dữ liệu(PDF) 248 Page - NXP Semiconductors

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HCS08 bảng dữ liệu(HTML) 248 Page - NXP Semiconductors

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Timer/PWM Module (S08TPMV3)
MC9S08SG8 MCU Series Data Sheet, Rev. 8
248
Freescale Semiconductor
16.3.2
TPM-Counter Registers (TPMxCNTH:TPMxCNTL)
The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.
Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where
they remain latched until the other half is read. This allows coherent 16-bit reads in either big-endian or
little-endian order which makes this more friendly to various compiler implementations. The coherency
mechanism is automatically restarted by an MCU reset or any write to the timer status/control register
(TPMxSC).
Reset clears the TPM counter registers. Writing any value to TPMxCNTH or TPMxCNTL also clears the
TPM counter (TPMxCNTH:TPMxCNTL) and resets the coherency mechanism, regardless of the data
involved in the write.
Table 16-6. TPM-Clock-Source Selection
CLKSB:CLKSA
TPM Clock Source to Prescaler Input
00
No clock selected (TPM counter disable)
01
Bus rate clock
10
Fixed system clock
11
External source
Table 16-7. Prescale Factor Selection
PS2:PS1:PS0
TPM Clock Source Divided-by
000
1
001
2
010
4
011
8
100
16
101
32
110
64
111
128
76
54
32
1
0
R
Bit 15
14
13
12
11
10
9
Bit 8
W
Any write to TPMxCNTH clears the 16-bit counter
Reset
0
00
00
0
00
Figure 16-8. TPM Counter Register High (TPMxCNTH)



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