HCS08 datasheet(233/374 Pages) NXP

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Serial Communications Interface (S08SCIV4)

MC9S08JM60 Series Data Sheet, Rev. 5

Freescale Semiconductor

233

14.2.7

SCI Data Register (SCIxD)

This register is actually two separate registers. Reads return the contents of the read-only receive data

buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also

involved in the automatic flag clearing mechanisms for the SCI status flags.

14.3

Functional Description

The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote

devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block.

The transmitter and receiver operate independently, although they use the same baud rate generator.

During normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and

processes received data. The following describes each of the blocks of the SCI.

14.3.1

Baud Rate Generation

As shown in Figure 14-12, the clock source for the SCI baud rate generator is the bus-rate clock.

TXINV1

Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output.

0 Transmit data not inverted

1 Transmit data inverted

ORIE

Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests.

0 OR interrupts disabled (use polling).

1 Hardware interrupt requested when OR = 1.

NEIE

Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests.

0 NF interrupts disabled (use polling).

1 Hardware interrupt requested when NF = 1.

FEIE

Framing Error Interrupt Enable — This bit enables the framing error flag (FE) to generate hardware interrupt

requests.

0 FE interrupts disabled (use polling).

1 Hardware interrupt requested when FE = 1.

PEIE

Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt

requests.

0 PF interrupts disabled (use polling).

1 Hardware interrupt requested when PF = 1.

1 Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle.

321

R7R6R5R4R3R2R1R0

T6T5T4

T3T2T1T0

Reset

000

Figure 14-11. SCI Data Register (SCIxD)

Table 14-7. SCIxC3 Field Descriptions (continued)

Field

Description

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