AD9689-2000EBZ datasheet(105/134 Pages) AD

105 / 134 page

Data Sheet

AD9689

Rev. A | Page 105 of 134

Addr.

Name

Bit(s) Bit Name

Setting

Description

Reset Access

0x0271 Signal Monitor

Period 0 (local)

[7:0] Signal monitor

period[7:0]

Bits[7:0] of the 24-bit value that sets the number of output

clock cycles over which the signal monitor performs its

operation. Only even values are supported.

0x80

R/W

0x0272 Signal Monitor

Period 1 (local)

[7:0] Signal monitor

period[15:8]

Bits[15:8] of the 24-bit value that sets the number of output

clock cycles over which the signal monitor performs its

operation. Only even values are supported.

0x0

R/W

0x0273 Signal Monitor

Period 2 (local)

[7:0] Signal monitor

period[23:16]

Bits[23:16] of the 24-bit value that sets the number of output

clock cycles over which the signal monitor performs its

operation. Only even values are supported.

0x0

R/W

0x0274 Signal monitor

status control

(local)

[7:5] Reserved

Reserved.

0x0

Result update

0x0

R/WC

Update signal monitor status registers, Register 0x0275 to

Reserved

Reserved.

0x0

[2:0] Result selection

0x1

R/W

001

Peak detector placed on status readback signals.

0x0275 Signal Monitor

Status 0 (local)

[7:0] Signal monitor

result[7:0]

Signal monitor status result. This 20-bit value contains the

status result calculated by the signal monitor block.

0x0

0x0276 Signal Monitor

Status 1 (local)

[7:0] Signal monitor

result[15:8]

Signal monitor status result.

0x0

0x0277 Signal Monitor

Status 2 (local)

[7:4] Reserved

Reserved.

0x0

[3:0] Signal monitor

result[19:16]

Signal monitor status result.

0x0

0x0278 Signal monitor

status frame

counter (local)

[7:0] Period count result[7:0]

Signal monitor frame counter status bits. The frame counter

increments whenever the period counter expires.

0x0

0x0279 Signal monitor

serial framer

control (local)

[7:2] Reserved

Reserved.

0x0

[1:0] Signal monitor SPORT

over JESD204B enable

0x0

R/W

Disabled.

Enabled.

0x027A SPORT over

JESD204B input

selection (local)

[7:6] Reserved

Reserved.

0x0

SPORT over JESD204B

input selection

Signal monitor serial framer input selection. When each

individual bit is a 1, the corresponding signal statistics

information is sent within the frame.

0x1

R/W

Disabled.

Peak detector data inserted in the serial frame.

Reserved

Reserved.

0x0

DDC Function Registers (See the Digital Downconverter (DDC) Section)

Table 50.

Addr.

Name

Bit(s) Bit Name

Setting

Description

Reset

Access

0x0300 DDC SYNC

control

DDC FTW/POW/MAW/

MBW update mode

Select DDC FTW/POW/MAW/MBW update mode.

0x0

R/W

Instantaneous/continuous update. FTW/POW/MAW/MBW values

are updated immediately.

FTW/POW/MAW/MBW values are updated synchronously when

the chip transfer bit (Register 0x000F, Bit 0) is set.

6:5

Reserved

Reserved.

0x0

DDC NCO soft reset

This bit can be used to synchronize all the NCOs inside the DDC

blocks.

0x0

R/W

Normal operation.

DDC held in reset.

[3:2] Reserved

Reserved.

0x0

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