AD9689-2000EBZ datasheet(85/134 Pages) AD

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Data Sheet

AD9689

Rev. A | Page 85 of 134

MULTICHIP SYNCHRONIZATION

The flowchart in Figure 147 shows the internal mechanism for

multichip synchronization in the AD9689. There are two methods

by which multichip synchronization can take place, as determined

by the synchronization mode bit (Register 0x01FF, Bit 0). Each

method involves different applications of the SYSREF signal.

NORMAL MODE

The default sate of the chip synchronization mode bit is 0, which

configures the AD9689 for normal chip synchronization. The

JESD204B standard specifies the use of SYSREF to provide for

deterministic latency within a single link. This same concept,

when applied to a system with multiple converters and logic

devices, can also provide multichip synchronization referred to as

normal mode (see Figure 147). Following the process in the

flowchart ensures that the AD9689 is configured appropriately. The

user must also consult the logic devices user IP guide to ensure

that the JESD204B receivers are configured appropriately.

TIMESTAMP MODE

For all AD9689 full bandwidth operating modes, the SYSREF

input can also be used to timestamp samples, another method

by which multiple channels and multiple devices can achieve

synchronization. This method is especially effective when

synchronizing multiple devices to one or more logic devices. The

logic devices buffer the data streams, identify the timestamped

samples, and align them. When the synchronization mode bit

(Register 0x01FF, Bit 0) is set to 1, the timestamp method is

used for synchronization of multiple channels and/or devices.

In this mode, SYSREF resets the sample dividers and the

JESD204B clocking. When the chip sync mode is set to 1, the

clocks are not reset; instead, the coinciding sample is timestamped

using the JESD204B control bits of that sample. To operate in

timestamp mode, these additional settings are necessary:

•

Continuous or N-shot SYSREF must be enabled

(Register 0x0120, Bits[2:1] = 1 or 2 decimal).

•

At least one control bit must be enabled (Register 0x058F,

Bits[7:6] = 1, 2, or 3 decimal).

•

Set the function for one of the control bits to SYSREF:

0, Register 0x0559, Bits[7:4] = 5 decimal if using Control

Bit 1, Register 0x055A, Bits[3:0] = 5 decimal if using

Control Bit 2.

Figure 146 shows how the input sample coincident with

SYSREF is timestamped and ultimately output from the ADC.

In this example, there are two control bits, and Control Bit 0 is

the bit indicating which sample was coincident with the

SYSREF rising edge. Note that the pipeline latencies for each

channel are identical. If so desired, the SYSREF± timestamp

delay register (Register 0x0123) can be used to adjust the timing

of which sample is time stamped.

Note that time stamping is not supported by any AD9689

operating modes that use decimation.

AINA

AINB

ENCODE CLK

SYSREF

CHANNEL B

CHANNEL A

N – 1

N + 1

N + 2

N + 3

N – 1

N + 1

N + 2

N + 3

N – 1

N + 1

2 CONTROL BITS

CONTROL BIT 0 USED TO

TIME STAMP SAMPLE N

14-BIT SAMPLES OUT

N + 2

N + 3

N – 1

N + 1

N + 2

N + 3

Figure 146. AD9689 Timestamping Example—CS = 2 (Register 0x058F, Bits[7:6] = 2 Decimal), Control Bit 0 is SYSREF (Register 0x0559, Bits[3:0] = 5 Decimal)

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