AD9689-2000EBZ datasheet(34/134 Pages) AD

34 / 134 page

AD9689

Data Sheet

Rev. A | Page 34 of 134

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. The AD9689 contains an

internal clock divider and a duty cycle stabilizer comprised of

DCS1 and DCS2, which is enabled by default. In applications

where the clock duty cycle cannot be guaranteed to be 50%, a

higher multiple frequency clock along with the usage of the

clock divider is recommended.

When it is not possible to provide a higher frequency clock, it is

recommended to turn on the DCS using Register 0x011C and

AD9689 clock inputs. The output of the divider offers a 50% duty

cycle, high slew rate (fast edge) clock signal to the internal ADC.

See the Memory Map section for more details on using this feature.

Input Clock Divider

The AD9689 contains an input clock divider with the ability to

divide the input clock by 1, 2, or 4. Select the divider ratios

using Register 0x0108 (see Figure 92).

The maximum frequency at the CLK± inputs is 6 GHz, which is

the limit of the divider. In applications where the clock input is

a multiple of the sample clock, take care to program the appropriate

divider ratio into the clock divider before applying the clock

signal; this ensures that the current transients during device

startup are controlled.

REG 0x011C,

0x011E

REG 0x0108

CLK+

CLK–

÷2

÷4

Figure 92. Clock Divider Circuit

The AD9689 clock divider can be synchronized using the

external SYSREF± input. A valid SYSREF± signal causes the

clock divider to reset to a programmable state. This synchro-

nization feature allows multiple devices to have their clock

dividers aligned to guarantee simultaneous input sampling. See

the Memory Map Register Details section for more information.

Input Clock Divider ½ Period Delay Adjust

The input clock divider in the AD9689 provides phase delay in

increments of ½ the input clock cycle. Program Register 0x0109

to enable this delay independently for each channel. Changing

this register does not affect the stability of the JESD204B link.

Clock Fine Delay and Superfine Delay Adjust

Adjust the AD9689 sampling edge instant by writing to

of Register 0x0110 enable the selection of the fine delay, or the

fine delay with superfine delay. The fine delay allows the user to

delay the clock edges with 16-step or 192-step delay options.

The superfine delay is an unsigned control to adjust the clock

delay in superfine steps of 0.25 ps each.

the clock in 192 delay steps. Register 0x0111, Bits[7:0] offer the

user the option to delay the clock in 128 superfine steps. These

values can be programmed individually for each channel. To

use the superfine delay option, set the clock delay control in

controls available to the clock dividers within AD9689. It is

recommended to apply the same delay settings to the digital

delay circuits as are applied to the analog delay circuits to

maintain sample accuracy through the pipe.

PHASE

CH. B

PHASE

CH. A

CLK_DIV

0x0108

0x0109

FINE DELAY

0x0110,

0x0111,

0x0112

CHANNEL B

CHANNEL A

CLK INPUT

Figure 93. Clock Divider Phase and Delay Controls

The clock delay adjustment takes effect immediately when it is

enabled via SPI writes. Enabling the clock fine delay adjust in

of Register 0x0111 and Register 0x0112 can be changed without

affecting the stability of the JESD204B link.

Clock Coupling Considerations

The AD9689 has many different domains within the analog

supply that control various aspects of the data conversion. The

clock domain is supplied by Pin A4, Pin A5, Pin A10, Pin A11,

Pin B4, and Pin B11 on the analog supply, AVDD1 (0.975 V)

and Pin A6, Pin A9, Pin B6, Pin B7, Pin B8, Pin B9, Pin C6,

Pin C7, Pin C8, Pin C9, Pin D7, and Pin D8 on the ground

(AGND) side. To minimize coupling between the clock supply

domain and the other analog domains, it is recommended to

add a supply Q factor reduction circuitry for Pin A4 and Pin

A11, as well as Pin B4 and Pin B11, as shown in Figure 94.

100nF

10Ω

FERRITE BEAD

220Ω AT

100MHz

DCR ≤ 0.5Ω

A11

B11

AVDD1

PLANE

100nF

10Ω

FERRITE BEAD

220Ω AT

100MHz

DCR ≤ 0.5Ω

Figure 94. Q Factor Reduction Network Recommendation for the Clock

Domain Supply

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