AD9689-2000EBZ datasheet(84/134 Pages) AD

84 / 134 page

AD9689

Data Sheet

Rev. A | Page 84 of 134

Setting Deterministic Latency Registers

The JESD204B receiver in the logic device buffers data starting

on the LMFC boundary. If the total link latency in the system is

near an integer multiple of the LMFC period, it is possible that

from one power cycle to the next, the data arrival time at the

receive buffer may straddle an LMFC boundary. To ensure

deterministic latency in this case, a phase adjustment of the

LMFC at either the transmitter or receiver must be performed.

Typically, adjustments to accommodate the receive buffer are

made to the LMFC of the receiver. Alternatively, this adjustment

can be made in the AD9689 using the LMFC offset register

(Register 0x0578, Bits[4:0]). This adjustment delays the LMFC

in frame clock increments, depending on the F parameter

(number of octets per lane per frame). For F = 1, every fourth

setting (0, 4, 8, and so on) is valid and results in a four frame

clock shift. For F = 2, every other setting (0, 2, 4, and so on) is

valid and results in a two-frame clock shift. For all other values

of F, each setting results in a one-frame clock shift. Figure 144

shows that, when the link latency is near an LMFC boundary,

the local LMFC of the AD9689 can be adjusted to delay the data

arrival time at the receiver. Figure 145 shows how the LMFC of

the receiver is delayed to accommodate the receive buffer

timing. Consult the applicable JESD204B receiver user guide for

details on making this adjustment.

If the total latency in the system is not near an integer multiple

of the LMFC period or if the appropriate adjustments have been

made to the LMFC phase at the clock source, it is still possible

to have variable latency from one power cycle to the next. By

design, the AD9689 has circuitry in place to minimize this

variation from power-up to power-up. In this case, the user

must check for the possibility that the setup and hold time

requirements for the SYSREF signal are not being met, by

reading the SYSREF± setup/hold status bits (Register 0x0128).

This function is fully described in the SYSREF± Setup/Hold

Window Monitor section.

If reading Register 0x0128 indicates there may be a timing

problem, a few adjustments can be made in the AD9689.

Changing the SYSREF level that is used for alignment is possible

using the SYSREF± transition select bit (Register 0x0120, Bit 4).

Also, changing which edge of CLK± is used to capture SYSREF

can be done using the CLK± edge select bit (Register 0x0120,

Bit 3). Both of these options are described in the SYSREF

Control Features section. If neither of these measures helps to

achieve an acceptable setup and hold time, adjusting the phase

of SYSREF and/or the device clock (CLK±) may be required.

SYSREF ALIGNED

GLOBAL LMFC

DATA

(AT Tx INPUT)

DATA

(AT Rx INPUT)

Tx LOCAL LMFC

Tx LMFC MOVED (DELAYING THE ARRIVAL OF DATA RELATIVE

TO THE GLOBAL LMFC) SO THE RECIEVE BUFFER RELEASE TIME

IS ALWAYS REFERENCED TO THE SAME LMFC EDGE

LMFCTX DELAY TIME

POWER CYCLE VARIATION

ILAS

DATA

ILAS

DATA

Figure 144. Adjusting the JESD204B Tx LMFC in the AD9689

DATA

POWER CYCLE VARIATION

LMFCRX DELAY TIME

ILAS

SYSREF ALIGNED

GLOBAL LMFC

DATA

(AT Tx INPUT)

DATA

(AT Rx INPUT)

Rx LOCAL LMFC

Rx LMFC MOVED SO THE RECEIVE BUFFER RELEASE TIME

IS ALWAYS REFERENCED TO THE SAME LMFC EDGE

DATA

Figure 145. Adjusting the JESD204B Rx LMFC in the Logic Device

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