AD9689-2000EBZ datasheet(55/134 Pages) AD

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Data Sheet

AD9689

Rev. A | Page 55 of 134

DDC Mixer Description

When not bypassed (Register 0x0200 ≠ 0x00), the digital

quadrature mixer performs a similar operation to an analog

quadrature mixer. It performs the downconversion of input

signals (real or complex) by using the NCO frequency as a local

oscillator. For real input signals, a real mixer operation (with

two multipliers) is performed. For complex input signals, a

complex mixer operation (with four multipliers and two adders)

is performed. The selection of real or complex inputs can be

controlled individually for each DDC block using Bit 7 of the

DDC control registers (Register 0x0310, Register 0x0330,

DDC NCO + Mixer Loss and SFDR

When mixing a real input signal down to baseband, −6 dB of

loss is introduced in the signal due to filtering of the negative

image. An additional −0.05 dB of loss is introduced by the NCO.

The total loss of a real input signal mixed down to baseband is

−6.05 dB. For this reason, it is recommended that the user

compensate for this loss by enabling the 6 dB of gain in the gain

stage of the DDC to recenter the dynamic range of the signal

within the full scale of the output bits (see the DDC Gain Stage

(Optional) section).

When mixing a complex input signal (where I and Q DDC

inputs come from the different ADCs) down to baseband, the

maximum value each I/Q sample is able to reach is 1.414 × full

scale, after the sample passes through the complex mixer. To

avoid overrange of the I/Q samples and to keep the data bit

widths aligned with real mixing, −3.06 dB of loss is introduced

in the mixer for complex signals. An additional −0.05 dB of loss

is introduced by the NCO. The total loss of a complex input

signal mixed down to baseband is −3.11 dB.

The worst case spurious signal from the NCO is greater than

102 dBc SFDR for all output frequencies.

DDC DECIMATION FILTERS

After the frequency translation stage, there are multiple

decimation filter stages that reduce the output data rate. After

the carrier of interest is tuned down to dc (carrier frequency =

0 Hz), these filters efficiently lower the sample rate, while

providing sufficient alias rejection from unwanted adjacent

carriers around the bandwidth of interest.

Figure 118 shows a simplified block diagram of the decimation

filter stage, and Table 16 describes the filter characteristics of

the different finite impulse response (FIR) filter blocks.

Table 17 shows the different filter configurations selectable by

including different filters. In all cases, the DDC filtering stage

provides 80% of the available output bandwidth, <±0.005 dB of

pass-band ripple and >100 dB of stop band alias rejection.

DECIMATION FILTERS

DCM = 3

FIR = FINITE IMPULSE RESPONSE FILTER

DCM = DECIMATION

HB1

FIR

TB1

FIR

DCM = 2

HB4

FIR

TB2

FIR

DCM = 3

DCM = 2

HB4

FIR

DCM = 2

FB2

FIR

DCM = 5

FB2

FIR

DCM = 5

DCM = 2

TB1

FIR

HB1

FIR

DCM = 3

TB2

FIR

HB3

FIR

DCM = 2

HB2

FIR

DCM = 2

HB3

FIR

DCM = 2

HB2

FIR

DCM = 2

NCO

AND

MIXERS

(OPTIONAL)

NOTES

1. TB1 IS ONLY SUPPORTED IN DDC0 AND DDC1

Figure 118. DDC Decimation Filter Block Diagram

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