AD9689-2000EBZ datasheet(30/134 Pages) AD

30 / 134 page

AD9689

Data Sheet

Rev. A | Page 30 of 134

Input Common Mode

The analog inputs of the AD9689 are internally biased to the

common-mode voltage, as shown in Figure 82. The common-

mode buffer has a limited range in that the performance suffers

greatly if the common-mode voltage drops by more than 50 mV on

either side of the nominal value.

For dc-coupled applications, the recommended operation procedure

is to export the common-mode voltage to the VREF pin using

the SPI writes listed in this section. The common-mode voltage

must be set by the exported value to ensure proper ADC

operation. Disconnect the internal common-mode buffer from

the analog input using Register 0x1908.

When performing SPI writes for dc coupling operation, use the

following register settings in order:

1. Set Register 0x1908, Bit 2 to disconnect the internal

common-mode buffer from the analog input. Note that

this is a local register.

2. Set Register 0x18A6 to 0x00 to turn off the voltage reference.

3. Set Register 0x18E6 to 0x00 to turn off the temperature

diode export.

4. Set Register 0x18E3, Bit 6 to 1 to turn on the VCM export.

5. Set Register 0x18E3, Bits[5:0] to the buffer current setting

(Register 0x1A4C and Register 0x1A4D) to improve the

accuracy of the common-mode export.

Figure 81 shows the block diagram of a dc-coupled application.

ADC

AMP A

VOCM

VREF

VCM EXPORT SELECT

SPI REGISTERS 0x1908,

0x18A6, 0x18E3, 0x18E6)

ADC

AMP B

Figure 81. DC-Coupled Application Using the AD9689

Analog Input Buffer Controls and SFDR Optimization

VIN+x

100Ω

AVDD3

0.3pF

AVDD3

VIN–x

AVDD3

REG

(0x0008,

0x1908)

REG (0x0008, 0x1A4C,

0x1A4D, 0x1910)

AVDD3

0.3pF

Figure 82. Analog Input Controls

The AD9689 input buffer offers flexible controls for the analog

inputs, such as buffer current, dc coupling, and input full-scale

adjustment. All the available controls are shown in Figure 82.

Using Register 0x1A4C and Register 0x1A4D, the buffer behavior

on each channel can be adjusted to optimize the SFDR over various

input frequencies and bandwidths of interest. Use Register 0x1910

to change the internal reference voltage. Changing the internal

reference voltage results in a change in the input full-scale voltage.

When the input buffer current in Register 0x1A4C and

AVDD3 supply changes. This relationship is shown in Figure 83.

For a complete list of buffer current settings, see Table 46 and

Table 53.

0.17

0.18

0.19

0.2

0.21

0.22

0.23

0.24

0.25

0.26

400

500

600

700

BUFFER CURRENT SETTING (µA)

Figure 83. AVDD3 Current (IAVDD3) vs. Buffer Current Setting (Buffer Control 1

Setting in Register 0x1A4C and Buffer Control 2 Setting in Register 0x1A4D)

Table 10 shows the recommended values for the buffer current

for various Nyquist zones.

Table 10. SFDR Optimization for Input Frequencies

Product

Frequency

0x1A4C

and

0x1A4D

High

Frequency

Setting

0x1A48

AD9689-2600

DC to 1.3 GHz

Default

(300 µA)

Default (0x14)

1.3 GHz to 2.6 GHz

500 µA

Default (0x14)

>2.6 GHz

700 µA

0x54

AD9689-2000

DC to 1000 MHz

Default

(300 µA)

N/A1

1 GHz to 2 GHz

500 µA

N/A

>2 GHz

700 µA

N/A

N/A means not applicable.

AD9689-2000EBZ bảng dữ liệu(PDF) 30 Page - Analog Devices

AD9689-2000EBZ bảng dữ liệu(HTML) 30 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL