AD9689-2000EBZ datasheet(88/134 Pages) AD

88 / 134 page

AD9689

Data Sheet

Rev. A | Page 88 of 134

CLK

SYSREF

SYSREF SAMPLE PART 1

SYSREF SAMPLE PART 2 SYSREF SAMPLE PART 3

SYSREF SAMPLE PART 4

SYSREF SAMPLE PART 5

IGNORE FIRST THREE SYSREFs

SAMPLE THE FOURTH SYSREF

Figure 152. SYSREF Ignore Example (SYSREF Ignore Count, Register 0x0121, Bits[3:0] = 3)

SAMPLE CLOCK

SYSREF

SYSREF SKEW WINDOW = ±1

SYSREF SKEW WINDOW = ±2

SYSREF SKEW WINDOW = ±3

SYSREF SKEW WINDOW = 0

Figure 153. SYSREF Skew Window

When in continuous SYSREF mode (Register 0x0120, Bits[2:1] =

1), the AD9689 monitors the placement of the SYSREF leading

edge compared to the internal LMFC. If the SYSREF signal is

captured with a clock edge other than the one that is aligned

with the LMFC, the AD9689 initiates a resynchronization of the

link. Because input clock rates for AD9689 can be up to 4 GHz,

the AD9689 provides another SYSREF related feature that

makes it possible to accommodate periodic SYSREF signals

where cycle accurate capture is not feasible or not required. For

these scenarios, the AD9689 has a programmable SYSREF skew

window that allows the internal dividers to remain undisturbed

unless SYSREF occurs outside the skew window. The resolution

of the SYSREF skew window is set in sample clock cycles.

If the SYSREF negative skew window is 1 and the positive skew

window is 1, the total skew window is ±1 sample clock cycles,

meaning that, as long as SYSREF is captured within ±1 sample

clock cycle of the clock that is aligned with the LMFC, the link

continues to operate normally. If the SYSREF has jitter, which

can cause a misalignment between SYSREF and LMFC, this

feature allows the system to continue running without a

resynchronization, while still allowing the device to monitor for

larger errors not caused by jitter. For the AD9689, the positive

and negative skew window is controlled by the SYSREF window

negative bits (Register 0x0122, Bits[3:2]) and SYSREF window

positive bits (Register 0x0122, Bits[1:0]). Figure 153 shows

information on the location of the skew window settings relative to

Phase 0 of the internal dividers. Negative skew is defined as

occurring before the internal dividers reach Phase 0, and positive

skew is defined after the internal dividers reach Phase 0.

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