AD9689-2000EBZ datasheet(89/134 Pages) AD

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Data Sheet

AD9689

Rev. A | Page 89 of 134

SYSREF± SETUP/HOLD WINDOW MONITOR

To ensure a valid SYSREF signal capture, the AD9689 has a

SYSREF± setup/hold window monitor. This feature allows the

system designer to determine the location of the SYSREF± signals

relative to the CLK± signals by reading back the amount of

setup/hold margin on the interface through the memory map.

Figure 154 and Figure 155 show the setup and hold status values

for different phases of SYSREF±.

The setup detector returns the status of the SYSREF± signal

before the CLK± edge, and the hold detector returns the status

of the SYSREF signal after the CLK± edge. Register 0x0128

stores the status of SYSREF± and notifies the user if the

SYSREF± signal is captured by the ADC.

Table 36 shows the description of the contents of Register 0x0128

and how to interpret them.

VALID

REG 0x0128[3:0]

CLK±

INPUT

SYSREF±

INPUT

FLIP FLOP

HOLD (MIN)

FLIP FLOP

HOLD (MIN)

FLIP FLOP

SETUP (MIN)

0xF

0xE

0xD

0xC

0xB

0xA

0x9

0x8

0x7

0x6

0x5

0x4

0x3

0x2

0x1

0x0

Figure 154. SYSREF± Setup Detector

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