AD9689-2000EBZ datasheet(10/134 Pages) AD

10 / 134 page

AD9689

Data Sheet

Rev. A | Page 10 of 134

TIMING SPECIFICATIONS

Table 5.

Parameter

Description

Min

Typ

Max

Unit

CLK+ to SYSREF+ TIMING REQUIREMENTS

tSU_SR

Device clock to SYSREF+ setup time

−65

tH_SR

Device clock to SYSREF+ hold time

SPI TIMING REQUIREMENTS

tDS

Setup time between the data and the rising edge of SCLK

tDH

Hold time between the data and the rising edge of SCLK

tCLK for SPI Reads

Period of the SCLK

tCLK for SPI Writes

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHIGH for SPI Reads

Minimum period that SCLK must be in a logic high state

tHIGH for SPI Writes

Minimum period that SCLK must be in a logic high state

tLOW for SPI Reads

Minimum period that SCLK must be in a logic low state

tLOW for SPI Writes

Minimum period that SCLK must be in a logic low state

tACCESS

Maximum time delay between the falling edge of SCLK and

output data valid for a read operation

tDIS_SDIO

Time required for the SDIO pin to switch from an output to an

input, relative to the SCLK rising edge (not shown in Figure 4)

Timing Diagrams

CONVERTER0

SAMPLE N – 75 MSB

SERDOUT0–

SERDOUT0+

CLK–

CLK+

CLK–

CLK+

CONVERTER0

SAMPLE N – 75 LSB

SERDOUT1–

SERDOUT1+

CONVERTER0

SAMPLE N – 74 MSB

SERDOUT2–

SERDOUT2+

CONVERTER0

SAMPLE N – 74 LSB

SERDOUT3–

SERDOUT3+

CONVERTER1

SAMPLE N – 75 MSB

SERDOUT4–

SERDOUT4+

CONVERTER1

SAMPLE N – 75 LSB

SERDOUT5–

SERDOUT5+

CONVERTER1

SAMPLE N – 74 MSB

SERDOUT6–

SERDOUT6+

CONVERTER1

SAMPLE N – 74 LSB

SERDOUT7–

SERDOUT7+

APERTURE DELAY

N – 74

N – 73

N – 72

N – 1

N + 1

SAMPLE N

N – 75

ANALOG

INPUT

SIGNAL

SAMPLE N – 75 AND N – 74

ENCODED INTO ONE

8-BIT/10-BIT SYMBOL

Figure 2. Data Output Timing Diagram

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