AD9689-2000EBZ datasheet(44/134 Pages) AD

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AD9689

Data Sheet

Rev. A | Page 44 of 134

DIGITAL DOWNCONVERTER (DDC)

The AD9689 includes four digital downconverters (DDC0 to

DDC3) that provide filtering and reduce the output data rate. This

digital processing section includes an NCO, multiple decimating

FIR filters, a gain stage, and a complex to real conversion stage.

Each of these processing blocks has control lines that allow it to be

independently enabled and disabled to provide the desired

processing function. The digital downconverter can be configured

to output either real data or complex output data.

The DDCs output a 16-bit stream. To enable this operation, the

converter number of bits, N, is set to a default value of 16, even

though the analog core only outputs 14 bits. In full bandwidth

operation, the ADC outputs are the 14-bit word followed by two

zeros, unless the tail bits are enabled.

DDC I/Q INPUT SELECTION

The AD9689 has two ADC channels and four DDC channels.

Each DDC channel has two input ports that can be paired to

support both real and complex inputs through the I/Q crossbar

mux. For real signals, both DDC input ports must select the

same ADC channel (that is, DDC Input Port I = ADC Channel A

and DDC Input Port Q = ADC Channel A). For complex

signals, each DDC input port must select different ADC

channels (that is, DDC Input Port I = ADC Channel A and

DDC Input Port Q = ADC Channel B).

The inputs to each DDC are controlled by the DDC input selec-

tion registers (Register 0x0311, Register 0x0331, Register 0x0351,

and Register 0x0371). See Table 48 and Table 50 for information

on how to configure the DDCs.

DDC I/Q OUTPUT SELECTION

Each DDC channel has two output ports that can be paired to

support both real and complex outputs. For real output signals,

only the DDC Output Port I is used (the DDC Output Port Q is

invalid). For complex I/Q output signals, both DDC Output

Port I and DDC Output Port Q are used.

The I/Q outputs to each DDC channel are controlled by the

DDCx complex to real enable bit, Bit 3, in the DDCx control

registers (Register 0x0310, Register 0x0330, Register 0x0350,

and Register 0x0370).

The chip Q ignore bit in the chip mode register (Register 0x0200,

Bit 5) controls the chip output muxing of all the DDC channels.

When all DDC channels use real outputs, set this bit high to

ignore all DDC Q output ports. When any of the DDC channels

are set to use complex I/Q outputs, the user must clear this bit

to use both DDC Output Port I and DDC Output Port Q. For

more information, see Figure 126.

DDC GENERAL DESCRIPTION

The four DDC blocks extract a portion of the full digital

spectrum captured by the ADC(s). They are intended for IF

sampling or oversampled baseband radios requiring wide

bandwidth input signals.

Each DDC block contains the following signal processing

stages:

•

Frequency translation stage (optional)

•

Filtering stage

•

Gain stage (optional)

•

Complex to real conversion stage (optional)

DDC Frequency Translation Stage (Optional)

This stage consists of a phase coherent NCO and quadrature

mixers that can be used for frequency translation of both real or

complex input signals. The phase coherent NCO allows an

infinite number of frequency hops that are all referenced back

to a single synchronization event. It also includes 16 shadow

registers for fast switching applications. This stage shifts a

portion of the available digital spectrum down to baseband.

DDC Filtering Stage

After shifting down to baseband, this stage decimates the

frequency spectrum using multiple low-pass finite impulse

response (FIR) filters for rate conversion. The decimation

process lowers the output data rate, which in turn reduces the

output interface rate.

DDC Gain Stage (Optional)

Because of losses associated with mixing a real input signal

down to baseband, this stage compensates by adding an

additional 0 dB or 6 dB of gain.

DDC Complex to Real Conversion Stage (Optional)

When real outputs are necessary, this stage converts the

complex outputs back to real by performing an fS/4 mixing

operation plus a filter to remove the complex component of the

signal.

Figure 109 shows the detailed block diagram of the DDCs

implemented in the AD9689.

Figure 110 shows an example usage of one of the four DDC

channels with a real input signal and four half-band filters

(HB4 + HB3 + HB2 + HB1) used. It shows both complex

(decimate by 16) and real (decimate by 8) output options.

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